Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Utility Patent
1998-11-30
2001-01-02
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Utility Patent
active
06170072
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally related to a logic circuit verification apparatus and method for a semiconductor integrated circuit, and more particularly, to a logic circuit verification apparatus and method suitable for use in checking a logic circuit of a semiconductor integrated circuit which includes, as part of its circuitry, a circuit being already verified with regard to given points.
2. Description of the Background Art
In the process of designing a semiconductor integrated circuit, a logic circuit is verified as to whether or not the circuit operates normally after a circuit layout is determined. In the logic circuit verification stage, there are initially performed
(1) processing for calculating a delay time arising on the way of propagation of a signal through cells, in consideration of the layout of individual cells; and
(2) processing for calculating the standards (e.g., a set-up time and a hold time) by which registers included in the circuit operate normally, in consideration of the layout of individual registers. The standards will be hereinafter referred to as a “timing verification value.”
During the verification of the logic circuit, after completion of calculation of the foregoing delay time and the timing verification value, circuit operations are simulated through use of the thus-calculated values under circumstances where a clock signal and input data change at predetermined timing. Together with execution of the simulation, the logic of circuitry and timing at which signals are propagated are verified. Such a verification will be hereinafter referred to as a “logic-and-timing verification.”
Intellectual property (IP), such as a CPU core, is used for a portion of a semiconductor integrated circuit. The IP is a functional block which incorporates a plurality of combinational logic gates and registers and which has already been verified with regard to the logic and timing of the internal circuit. Such a functional block will be hereinafter referred to as a “core.”
In the designing process of a semiconductor integrated circuit including a core as part of its circuitry, a logic of a circuit in which a newly designed part and the core are in combination must be verified. In a conventional logic circuit verification, all the cells incorporated in the core are subjected to calculation of a delay time and a timing verification value. For this reason, there has been employed a method of checking the logic and timing of circuitry after calculation of a delay time and a timing verification value with regard to all the cells.
However, the internal logic and timing of the core has already been completed as mentioned previously. Accordingly, in checking whether or not a semiconductor integrated circuit comprising a newly designed circuit and the core in combination operates normally, not all the cells incorporated in the core necessarily have to be subjected to logic circuit verification. In this regard, the conventional method by which all the cells are subjected to logic circuit verification can be improved so as to shorten a time for verification.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the foregoing problem, and a general object of the present invention is to provide a novel and useful logic circuit verification apparatus and method for semiconductor device.
A more specific object of the present invention is to provide a logic circuit verification apparatus which shortens the time required for logic circuit verification, by extracting the cells required for verification from among a plurality of cells incorporated in the core and subjecting the extracted cells to the verification.
The above objects of the present invention are achieved by a logic circuit verification apparatus which performs logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core. The logic circuit verification includes a timing cell extraction section for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and a delay cell extraction section for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
The secondary object of the present invention is to provide a logic circuit verification method which enables shortening of the time required for logic circuit verification by extracting the cells required for verification from among a plurality of cells incorporated in the core and subjecting the extracted cells to the verification.
The above objects of the present invention are achieved by a method of logic circuit verification for performing logic circuit verification of a semiconductor integrated circuit which comprises a core having a plurality of combinational logic gates and a plurality of registers and whose internal circuit has already verified, and a new circuit to be combined with the core. The method includes a step for extracting from the cells of the core timing cells which are required to be subjected to timing verification when the core is used in combination with the new circuit; and a step for extracting from the cells of the core delay cells which are required to be subjected to time delay calculation when the core is used in combination with the new circuit.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5940370 (1999-08-01), Curtis et al.
patent: 6012833 (2000-01-01), Yoshikawa
patent: 6047247 (2000-04-01), Iwanishi et al.
patent: 4-288678 (1992-10-01), None
patent: 5-151301 (1993-06-01), None
patent: 6-60143 (1994-03-01), None
Inoshita Toshinori
Inoue Yoshio
Moriguchi Yasuo
Chung Phung M.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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