Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-25
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S228000, C438S303000, C438S231000, C438S595000
Reexamination Certificate
active
06277682
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuit manufacturing, and more particularly, to methods for simultaneously creating source-drain regions with different profiles for both low voltage devices and high voltage devices on the same substrate.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with the manufacture and formation of CMOS integrated circuit components for dual voltages, as an example.
Heretofore in this field, to improve reliability and reduce power consumption, the supply voltage of CMOS devices has been diminished with decreasing feature sizes and increasing performance. While circuit voltages are approaching 1 V, however, external supply voltages may remain at higher values from 1.5 to 5 V. This calls for mixed voltage CMOS technologies where the core circuits typically utilize very low voltages, such as a voltage between approximately 1.5 V to 1.8 V, and the input-output circuits typically use higher supply voltages, such as a voltage between approximately 3.3 V to 5 V.
The merger of low and high voltages becomes increasingly difficult to accomplish without an increase in the number of lithography steps. At the same time, the well known hot electron problems in the NMOS transistors at high drain voltages are of serious concern.
Various approaches have been aimed at reducing the voltage stress at the drains of N-transistors or reducing the intensity of electric fields in the channel region to minimize the generation of hot electrons, such as a normal lightly doped drain (LDD). A common approach to fabricating devices on the same substrate with different operating voltages is to reproduce existing process flows for low voltage and high voltage circuits separately. The result is differentiated gate length, gate oxide thickness, source-drain extensions and junctions, as shown in FIG.
1
. Thus, the low voltage circuits have short channel lengths, thin gate oxides, shallow source-drain extensions, and shallow source-drain areas, while the high voltage circuits have longer channel lengths, thicker gate oxides, deeper source-drain extensions, and deeper source-drain areas. This is, however, a very expensive and time consuming approach.
An alternative is to incorporate in high voltage circuits source-drain extensions and junctions that are suitable for low voltage circuits, as depicted in FIG.
2
. As shown in
FIG. 2
, the high voltage circuit has a longer channel length and thicker gate oxide than the low voltage circuit, but both have shallow source-drain areas and shallow source-drain extensions. In this case, the high voltage circuits would therefore have poor hot carrier reliability because of the high electric fields under the gate oxide by the junction. Electrostatic discharge protection may also be lacking because of the shallow junctions.
Deepening the junctions to alleviate this problem by increasing the implant energy, as shown in
FIG. 3
, degrades the performance of low voltage transistors because of increased junction capacitance and lower current drive. As shown in
FIG. 3
, the high voltage circuits have longer channel lengths and thicker gate oxides than the low voltage circuits, while both have intermediate source-drain areas and intermediate source-drain extensions. Thus, the dilemma between product reliability and economical efficiency calls for a process improvement to resolve these two conflicting factors.
SUMMARY OF THE INVENTION
What is needed is a method for designing and manufacturing integrated circuits using source-drain extensions only for low voltage devices and angular source-drain implants to create appropriate profiles of source-drain regions for high voltage devices.
In accordance with the present invention, a mask is applied to cover the high voltage device regions, allowing the low voltage device regions to be exposed to standard LDD or mid doped drain (MDD) implants to obtain source-drain extensions. Thereafter, the source-drain regions for both the low voltage device and the high voltage device are subject to a conditioned acute angular implant that creates appropriate profiles for high voltage device source-drain regions and fitting junctions for low voltage devices, which, in combination with the source-drain extensions, assures the performance of the low voltage devices. Implant conditions such as energy, dose, angle, and thermal drive may be tailored in accordance with the desired final product.
Moreover, there is no need to process the source-drain regions of the low voltage device and the high voltage device in separate steps to achieve their distinct features, resulting in economic fabrication of a mixed voltage CMOS integrated circuit by reducing the number of processing steps.
REFERENCES:
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5606191 (1997-02-01), Wang
patent: 5686324 (1997-11-01), Wang et al.
patent: 5827747 (1998-10-01), Wang et al.
patent: 6020231 (2000-02-01), Wang et al.
patent: 6100125 (2000-08-01), Hulfachor et al.
Anya Igwe U.
Brady W. James
Hoel Carlton H.
Smith Matthew
Telecky , Jr. Frederick J.
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