Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-07
2001-03-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000
Reexamination Certificate
active
06197631
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device and fabricating method thereof, and more particularly, to a semiconductor storage device and fabricating method thereof provided with a capacitor that uses a ferroelectric substance as a dielectric film.
A prior art non-volatile memory that uses a ferroelectric substance is shown in FIG.
3
. The prior art ferroelectric memory is constructed of at least one switching transistor and at least one ferroelectric capacitor. Similar to the CMOS (Complementary Metal Oxide Semiconductor) process of the conventional DRAM (Dynamic Random Access Memory), after forming a switching transistor in an active region surrounded by an element isolation region and forming a lower electrode corresponding to a drive line on the element isolation region, a ferroelectric substance is formed. The ferroelectric capacitor exhibits a hysteretic behavior of charged electrons with respect to an application electric field.
The ferroelectric film has a spontaneous polarization even though the application electric field is removed, and therefore, information (1 or 0) is stored depending on the direction of this polarization. Taking advantage of this property, a non-volatile memory capable of retaining the information when the power supply is turned off can be achieved. For the application of the ferroelectric capacitor to a memory, there is necessitated about 5 &mgr;C/cm
2
charge on the capacitor since positive and negative threshold voltages for inverting the polarization are equal to each other and a difference between the amount of inverted charges and the amount of non-inverted charges is detected by a sensing amplifier of a semiconductor memory.
After forming the ferroelectric capacitor, there are simultaneously processed an upper plate electrode, a PZT film and a drive line into respective specified shapes. A bit line is electrically connected to one source/drain region, while the other source/drain region is electrically connected to a plate electrode of the ferroelectric capacitor by way of wiring.
For the ferroelectric substance, there is employed lead zirconate titanate (PbZr
x
Ti
1-x
O
3
, referred to as PZT hereinafter), bismuth layered compound (SrBi
4
Ti
4
O
15
, SrBi
2
Ta
2
O
9
) or the like as a material that satisfies the aforementioned characteristics. For the electrode material, there are employed PtRh and PtRhO
x
that have a good lattice bondability to the PZT film and an excellent oxidation resistance or RuO
2
, IrO
2
and LaSrCoO that are oxides and have the feature of electrical conductivity. After the formation of the ferroelectric capacitor, an interlayer insulating film is formed and the elements are interconnected by means of metal wiring. For the interlayer insulating film, there is employed the raw material of silane gas or TEOS (tetraethoxysilane), and a silicon oxide film or a silicon nitride film is formed by the CVD (Chemical Vapor Deposition) method.
A memory provided with a transistor as described above is normally subjected to a heat treatment within a temperature range of 400 to 450° C. in an inert gas atmosphere containing hydrogen after the completion of the final process of metal wiring or protecting film formation. This process is to obtain stable transistor characteristics through a reduction in the interface state density of the gate oxide film by vanishing a defect at the interface between the gate oxide film of the transistor and the substrate with diffused hydrogen.
A prior art technique as disclosed in the prior art reference of Japanese Patent Laid-Open Publication No.
HEI 7-273297 will be described below with reference to FIG.
3
.
First, an element isolation region
42
is formed on the surface of a semiconductor substrate
41
, and thereafter, diffusion regions of a source
43
and a drain
44
and a switching transistor
47
having a gate electrode
46
to be formed on the substrate
41
via a gate insulating film
45
are formed.
Next, a BPSG film (Boro-Phospho Silicate Glass film)
48
is formed as an interlayer insulating film, and further a titanium adhesion layer
49
having a film thickness of 20 nm, a Pt lower electrode
51
having a film thickness of 200 nm, a ferroelectric film
52
having a film thickness of 250 nm and a Pt upper electrode
53
having a film thickness of 200 nm are successively formed on the BPSG film
48
. The lower electrode
51
, the ferroelectric film
52
and the upper electrode
53
constitute a capacitor
50
.
Next, a first protecting film
54
made of silicon oxide comprised of SOG (spin-on glass) is formed to a film thickness of 200 nm, and a second protecting film
55
is formed to a film thickness of 220 nm by application heat treatment of a MOD (Metal Organic Decomposition) solution having the same composition as that of the material of the ferroelectric thin film
52
on the first protecting film
54
. The second protecting film
55
is baked under the same processing conditions as those of the ferroelectric film
52
.
Further, an interlayer insulating film
56
is formed to a film thickness of 300 nm on the second protecting film
55
by silane thermal decomposition achieved by LPCVD (Low Pressure Chemical Vapor Deposition). Openings
57
are formed through the first protecting film
54
, the second protecting film
55
, the interlayer insulating film
56
and the BPSG film
48
, which are corresponding to the source
43
and the drain
44
of the switching transistor
47
. A source lead wire
58
and a drain lead wire
59
are formed through these openings
57
. Openings
57
, which are corresponding to the upper electrode
53
and the lower electrode
51
, are also formed through the first protecting film
54
, the second protecting film
55
and the interlayer insulating film
56
. The drain lead wire
59
and an upper electrode lead wire
60
are electrically connected to each other through these openings
57
.
After the formation of the capacitor
50
, the interlayer insulating film
56
to be employed between the multilayer wiring lines
60
,
59
and
58
made of aluminum or the like or the protecting films
54
and
55
to be formed after the completion of the wiring lines must be formed at a substrate temperature of about 400° C. taking the reaction of the aluminum wiring lines
60
,
59
and
58
with the silicon substrate
41
and the reliability of the aluminum wiring lines
60
,
59
and
58
into consideration. For this reason, the interlayer insulating film
56
and the protecting films
54
and
55
have conventionally been formed of the raw material of silane or TEOS (tetraethoxysilane) by the plasma CVD method capable of forming the films at low temperature.
However, the interlayer insulating film
56
formed of silane or TEOS by the plasma CVD method contains a large amount of hydrogen. The hydrogen is dissociated by heat treatment at a temperature of about 400° C. after the formation of the protecting films
54
and
55
, diffused into the elements and activated by the Pt upper electrode
53
of the ferroelectric capacitor
50
. When the activated hydrogen reaches an interface of the ferroelectric film
52
, a reduction effect occurs on the ferroelectric film
52
side, as a consequence of which oxygen in the film
52
is pulled out to destroy the dielectric property. If this phenomenon progresses, then the ferroelectric characteristic of the ferroelectric film
52
deteriorates to cause an increase in the leak current. Furthermore, the heat treatment is performed in an inert gas atmosphere containing hydrogen after the formation of the upper electrode
53
in the above prior art, and therefore, the deterioration in the ferroelectric characteristic and an increase in the leak current occur similarly.
If a thin film
55
equivalent to the ferroelectric substance in terms of composition and crystalline structure is used as a hydrogen interrupting protecting film, then the protecting film is hard to be flattened. This leads to a problem that a separation from the insulating film on the protecting film occurs
Elms Richard
Morrison & Foerster / LLP
Pyonin Adam
Sharp Kabushiki Kaisha
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