Method of fabricating a narrow bit line structure

Details Method of fabricating a narrow bit line structure Method of fabricating a narrow bit line structure

1999-08-31

2001-03-06

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S719000, C438S720000, C438S721000

Reexamination Certificate

active

06197630

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a bit line structure, and particularly to a method of fabricating a narrow bit line structure.
2. Description of the Prior Art
Recently, ultra large scale integration (ULSI) semiconductor technologies have dramatically increased the integrated circuit density on the chips formed on the semiconductor substrate. This increase in circuit density has resulted from downsizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching, and other semiconductor technology innovations. However, future requirements for even greater circuit density is putting additional demand on the semiconductor processing technologies and on device electrical requirements.
The rapidly increasing integrated circuit in the number of cells on the DRAM chip, it is becoming increasingly difficult to fabricate a narrow bit line structure.
FIGS. 1A and 1B
shows the cross-sectional view of a traditional bit line structure
160
. At first, the polysilicon layer
120
is formed on the interpoly dielectric layer
110
and the landing pad
100
. Afterwards, the tungsten silicide layer
130
is formed on the polysilicon layer
120
. Next, the silicon-oxy-nitride layer
140
is formed on the tungsten silicide layer
130
. Finally, the defined photoresist layer
150
is formed, having a width about 0.2 &mgr;m, as shown in FIG.
1
A. However, a portion of silicon-oxy-nitride layer
140
, a portion of the tungsten silicide layer
130
, and a portion of the polysilicon layer
120
are etched to expose the land pad
100
and the interpoly dielectric layer
110
, using the defined photoresist layer
150
as a mask. Then, the defined photoresist layer
150
is removed on silicon-oxy-nitride layer
140
. Finally, the bit line structure
160
is formed on the landing pad
100
, as shown in FIG.
1
B. Due to this bit line structure
160
will not obtain the linewidth of 0.1 &mgr;m. Thus, this present invention is disclosed by applying novel processes, and improving the disadvantage.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a narrow bit line structure that substantially reduces linewidth. In one embodiment, the fabrication process includes the steps as follows. At first, the interpoly dielectric layer is formed over the metal-oxide-semiconductor field effect transistor. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer is formed on the interpoly dielectric layer and the landing pad. The tungsten silicide layer is formed on the first polysilicon layer. Next, the silicon-oxy-nitride layer is formed on the tungsten silicide layer. Then the second polysilicon layer is formed on the silicon-oxy-nitride layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall and on the silicon-oxy-nitride layer. The silicon oxide layer is deposited on the second polysilicon layer, the polysilicon spacer, and the silicon-oxy-nitride layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer. The second polysilicon layer, the polysilicon spacer, a portion of the silicon-oxy-nitride layer, a portion of the tungsten silicide layer, and a portion of the first polysilicon layer is continuously etched to expose the interpoly dielectric layer, using the silicon oxide layer as a hard mask. Afterwards, the silicon oxide layer is removed on the silicon-oxy-nitride layer. Finally, the narrow bit line structure is formed over the landing pad.


REFERENCES:
patent: 5700731 (1997-12-01), Lin et al.
patent: 5858829 (1999-01-01), Chen
patent: 6097051 (2000-08-01), Torii et al.
patent: 6100126 (2000-08-01), Chen et al.
patent: 6121085 (2000-09-01), Liang et al.

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