Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-28
2001-06-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S328000
Reexamination Certificate
active
06245610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an N-well or a P-well at a floating stage. More particularly, the invention relates to a method of protecting an N-well or P-well at a floating stage from being damaged by plasma without degrading electrical characteristics or performance.
2. Description of the Related Art
In an integrated circuit, after the formation of certain devices, there are still some processes to be performed to complete the circuit layout. For example, after a PMOS or an NMOS is formed on a substrate, to obtain an electrical connection between PMOS or NMOS and other devices or terminals, a conductive layer is formed and patterned. While patterning the conductive layer, an etching step is inevitable. The plasma or other charged particles used to etch the conductive layer very often damage the NMOS or PMOS formed on the substrate.
Similarly, for a substrate comprising a floating well having a conductivity type different from that of the substrate, that is, the well at a floating stage without electrically connecting to other component or device, the above mentioned plasma damage is also very likely to happen.
Considering a P type substrate comprises an N-well therein. The P type substrate is typically placed on or connected to a chuck which is grounded. Therefore, any charged carriers coming from the plasma can be directed to the chuck to be grounded via the P type substrate. However, if the charged carriers are absorbed by the N-well, these carriers have no path to dissipate or to be neutralized. As a result, the charged carriers accumulate in the N-well, and thus, the electrical characteristics of the N-well or even the quality of gate oxide formed thereon is seriously degraded.
In addition, since the N-well is formed in and adjacent to the P type substrate, plus that the P type substrate is grounded, a potential difference is caused between the P-type substrate and the N-well. Therefore, if a protection structure across the N-well and the P type substrate is formed to resolve the problems caused by plasma damage, with this potential difference, the performance and electrical characteristics will be degraded.
SUMMARY OF THE INVENTION
The method provides a method which uses a big via pattern plus an over etching step for a top metal layer formed for interconnect. As a result, the originally connected components in a first conductive type substrate and in the second conductive type well formed for the purpose of protection from plasma damage is open while the top metal layer is patterned. Therefore, during the fabrication process, the second type well is not damaged while the electrical properties of the devices or circuit is enhanced. The gate oxide layers formed on both the first conductive type substrate and the second type well thus maintain similar good quality.
A method of protecting a floating well is provided in the invention. In a substrate of a first conductive type, a second conductive type well is formed. A first heavily doped region of the first conductive type and a second heavily doped region of the second conductive type are formed in the substrate and the well, respectively. A first dielectric layer is formed on the substrate and the well. Within the dielectric layer, there are at least two plugs to couple with the first and the second heavily doped region respectively. These two plugs are further electrically connected with each other by the formation of a bottom metal layer within the dielectric layer. The dielectric layer is patterned to formed first via hole or contact window openings with various sizes, and one of the first openings is formed to align over and expose the first metal layer. A glue layer is formed on the dielectric layer, so that a portion of the first openings with sizes large enough have the glue layer conformal thereto, while the other portion of the first openings with sizes small enough are filled with the glue layer. A chemical mechanical polishing step is performed to remove the glue layer on a top surface of the first dielectric layer as well as the glue layer on the portion of the first openings which are substantially large enough, such as the first opening exposing the first metal layer. Therefore, the first metal layer is exposed. A second dielectric layer is formed and patterned on the first dielectric layer. The second dielectric layer has second openings with various sizes, while one of the second openings exposes the first metal layer. A glue layer is formed on the second dielectric layer and surfaces of the second openings. Again, while a portion of the second openings has substantially small sizes, the portion of the second openings is filled thereby. A second metal layer is formed and patterned on the second dielectric layer. The second metal layer is further over etched until the first metal layer under a bottom of one of the second openings that aligned over the first metal layer is open.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Huang-Lu Shiang
Lee Tzung-Han
Wang Mu-Chun
Gurley Lynne A.
Niebling John F.
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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