Method for making the bottom electrode of a capacitor

Details Method for making the bottom electrode of a capacitor Method for making the bottom electrode of a capacitor

2000-03-22

2001-06-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S244000, C438S245000, C438S246000, C438S247000, C438S248000, C438S386000, C438S387000, C438S388000, C438S389000, C438S390000, C438S391000, C438S392000

Reexamination Certificate

active

06245612

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for making buried bottom electrodes, and particularly relates to a method for making the bottom electrode of a buried capacitor, which can improve the vertical leakage current.
2. Description of the Prior Art
Deep trench has been widely used in advanced DRAM technology, wherein the capacitors are buried in the trench. The electronic property of the DRAM is based on the charge-storing capacity, which is determined by the area of the electrodes of the capacitor. Recently, the effective region for bottom electrodes of the buried capacitors can be defined by photolithography and etching processes. The processes for fabricating the traditional buried capacitor are illustrated in
FIG. 1A
to FIG.
1
E.
Referring to
FIG. 1A
, a P-type Si substrate is provided. A pad oxide layer
110
with a thickness of about 45 Å is formed on the substrate
100
by way of thermal oxidation. A silicon nitride layer
120
and a TEOS layer
130
are deposited on the pad oxide layer
110
in series. Then, a photoresist pattern
140
with an opening for etching is formed on the TEOS layer
130
by photolithography and etching processes.
Referring to
FIG. 1B
, by using the photoresist pattern
140
as an etching mask, the exposed TEOS layer
130
within the opening, and the silicon nitride layer
120
, the pad oxide layer
110
underlying the exposed TEOS layer
130
are removed by dry-etching to pattern a hard mask
150
. Then, the photoresist pattern
140
is removed. The substrate
100
unshielded by the hard mask
150
is etched to form a trench
160
with a depth ranging from 7 &mgr;pm to 8 &mgr;m.
Referring to
FIG. 1C
, a N-type Si-glass, such as AsSG, is deposited to comfortably cover the TEOS layer
130
and the side wall of the trench
160
. Then, a photoresist layer
180
is formed on the Si substrate
170
, and filled the trench
160
.
Referring to
FIG. 1D
, a photoresist
180
with a thickness of about 4~6 &mgr;m and the remained N-type Si glass
170
are left on the bottom of the trench
160
to define the predetermined region
185
for the bottom electrode by etching back the photoresist
180
and the N-type Si glass
170
.
Referring to
FIG. 1E
, a TEOS layer with a thickness ranging from 100 Å~300 Å (unshown) is deposited after removing the photoresist layer
180
. Then, an annealing treatment is applied to drive the N-type impurities within the Si-glass
170
to diffuse into the bottom electrode region
185
through the side wall of the trench
160
, thus a bottom electrode
190
consisting of N-type diffusion region is generated.
However, when wet etching is used to define the predetermined region
185
for the bottom electrode
190
, some remains of the N-type Si-glass
170
will be left beside the predetermined region
185
for the bottom electrode, and particularly the side wall of the trench upside the predetermined region
185
for the bottom electrode
190
. The N-type impurities within the remains left beside the predetermined region
185
for the bottom electrode
190
will be driven to diffuse into the P-type substrate
100
during annealing, thus a non-desired N-type diffusion region connecting to the bottom electrode
190
is generated. Accordingly, a serious leakage current will appear in the buried capacitor comprising the bottom electrode made according to the above-mentioned method.
SUMMARY OF THE INVENTION
The object of the present invention is to reduce the above-mentioned leakage current and to provide a method for making the bottom electrode of a buried capacitor. This present method is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si-glass remained in non-bottom electrode region from driving into the substrate during annealing. Thus non-desired diffusing region connecting to the bottom electrode will be generated. Consequently, the leakage current existing in conventional buried capacitor will be effectively reduced according to the method disclosed in this present invention.


REFERENCES:
patent: 5618751 (1997-04-01), Golden et al.
patent: 5981332 (1999-11-01), Mandelman et al.
patent: 6057216 (2000-05-01), Economikos et al.
patent: 6090661 (2000-07-01), Perng et al.

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