Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-13
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S269000, C438S424000, C438S524000
Reexamination Certificate
active
06214680
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the method of fabrication of integrated circuit devices, and more particularly, to a method of forming a sub-quarter-micron MOSFET structure in the fabrication of integrated circuits.
(2) Description of the Prior Art
In sub-quarter-micron MOSFET architecture, it is necessary to use ultra-shallow source and drain extension regions. Low energy ion implantation is typically used to form such regions.
For example,
FIG. 1
illustrates a semiconductor substrate
10
, preferably composed of monocrystalline silicon. A layer of silicon oxide
12
is formed on the surface of the substrate. A polysilicon layer is deposited and patterned to form gate electrode
16
. A typical LDD (lightly doped source and drain) structure
24
is formed by an LDD mask implant followed by deposition of the spacer oxide
18
and then a source/drain mask implant
20
. Lightly doped source and drain regions
24
lie under the spacers
18
as shown in FIG.
1
.
Gate critical dimension (CD) reproducibility has been a concern of all of the sub-micron technologies. Minimum gate length corresponds to the minimum feature size of any technology generation; that is, the edges of the lithography tool capability. Therefore, considerable relative variations of a gate CD are inevitable. At the same time, device characteristics strongly depend on the gate length.
U.S. Pat. No. 5,447,874 to Grivna et al teaches a method of forming a MOSFET device employing a dual metal gate formed in an oxide opening. Using a chemical mechanical polishing step to planarize the surface eliminates the problems encountered in etching different metals. U.S. Pat. No. 5,856,225 to Lee et al teaches a method of forming a MOSFET device where the source/drain regions are built prior to the implantation of the channel region under the gate. This allows more precise control of the source/drain positions, thereby controlling the electrical parameters of the MOSFET device. U.S. Pat. No. 5,393,681 to Witek et al teaches a method of forming a vertically raised transistor using selective epitaxial growth (SEG) to form the channel region of a MOSFET. U.S. Pat. No. 5,391,506 to Tada et al teaches a method for forming a transistor in a projection formed in the substrate. U.S. Pat. No. 5,624,863 to Helm et al teaches a method where the source and drain of a MOSFET are formed using out-diffusion from a doped silicon plug into the substrate.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a MOSFET device having a raised source/drain structure.
Another object of the present invention is to provide a method of fabricating a MOSFET device having a raised source/drain structure using selective epitaxial growth (SEG).
Yet another object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device having a source and drain extension structure wherein the source/drain dopant concentrations are precisely controlled.
A further object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device wherein the particle implant damage to the gate oxide is minimized.
Yet another object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device wherein the contact spacing is wider. This allows use of a thicker metal salicide reducing the sheet resistance of the source, drain and gate regions. The wider spacing also reduces inter-electrode leakage.
A still further object of the present invention is to provide a method of fabricating a sub-quarter-micron MOSFET device having a flat surface topology allowing for better step coverage during subsequent processing.
In accordance with the objects of this invention, a new method of fabricating a sub-quarter micron MOSFET device is achieved. A semiconductor substrate is provided. Shallow-trench isolation (STI) regions, for example, are formed in this substrate. An oxide layer is provided overlying both the substrate and the STI regions. The oxide layer is patterned and etched exposing two regions of the substrate. A selective epitaxial growth (SEG) is performed with intrinsic silicon covering the two exposed substrate regions formed during the previous step. These intrinsic silicon regions will eventually form the source and drain regions of the MOSFET. The oxide layer region between the two epitaxially grown intrinsic regions is then patterned and etched away exposing the substrate between the two intrinsic silicon regions. This is followed by a gate oxide deposition and a gate polysilicon deposition. Chemical mechanical polishing (CMP) is then performed to expose the top surface of the intrinsic silicon regions. An oxidation step is then performed consuming some of the silicon in the polysilicon gate and intrinsic silicon regions. Since the oxide is formed on the upper surface, more of the silicon is consumed from the top surfaces of the polysilicon gate and intrinsic silicon regions. This forms each of the polysilicon gate and intrinsic silicon regions into a trapezoidal shape where both are thinner on the upper portions of the structure and wider on the lower section. An oxide etch is then performed removing most of the gate oxide along the sidewalls of the polysilicon gate leaving V-shaped trenches along the sidewalls of the polysilicon gate. A low-angle ion implantation is performed forming source/drain extensions in the substrate area under the V-shaped trenches. An oxide is then deposited overlying the entire surface followed by a CMP planarization. A second implantation is performed to dope the two intrinsic silicon regions of the source/drain and polysilicon region. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.
REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.
patent: 4072545 (1978-02-01), De La Moneda
patent: 4331708 (1982-05-01), Hunter
patent: 4789644 (1988-12-01), Meda
patent: 5391506 (1995-02-01), Tada et al.
patent: 5393681 (1995-02-01), Witek et al.
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5624863 (1997-04-01), Helm et al.
patent: 5856251 (1999-01-01), Lee et al.
patent: 6090691 (2000-07-01), Ang et al.
patent: 6100161 (2000-08-01), Yu et al.
patent: 6110787 (2000-08-01), Chan et al.
Ang Ting Cheong
Loong Sang Yee
Ong Puay Ink
Quek Shyue Fong
Chartered Semiconductor Manufacturing Ltd.
Malsawma Lex H.
Pike Rosemary L.S.
Saile George O.
Smith Matthew
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