Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-17
2001-06-05
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06242297
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the same. More specifically, the present invention relates to a semiconductor device having memory cells and a method for fabricating that semiconductor device.
BACKGROUND ART
Static random access memories (SRAMS) are one type of known volatile semiconductor memory device. The SRAM typically has memory cells formed at points of intersection between complementary data lines (bit lines) and word lines arranged in a matrix fashion.
FIG. 32
is an equivalent circuit diagram showing a memory cell of a conventional SRAM. A typical circuit constitution of the SRAM will now be described with reference to FIG.
32
.
A memory cell of the conventional SRAM comprises two access transistors A
1
and A
2
, two driver transistors D
1
and D
2
, and two load transistors P
1
and P
2
. The two load transistors P
1
and P
2
and the two driver transistors D
1
and D
2
make up a flip-flop circuit. The flip-flop circuit constitutes two memory nodes N
1
and N
2
that are cross-coupled. The memory nodes N
1
and N
2
are in a bi-stable state involving one of two settings: either N
1
is High and N
2
Low, or N
1
is Low and N
2
High. The bi-stable state is maintained as long as power is supplied appropriately.
One source/drain region of each of the access transistors A
1
and A
2
is connected to the memory nodes N
1
and N
2
respectively, i.e., to input/output terminals of the flip-flop circuit. The other source/drain regions of the access transistors A
1
and A
2
are connected to bit lines. The gate electrodes of the access transistors A
1
and A
2
are connected to a word line. The word line controls the activation and deactivation of the access transistors A
1
and A
2
.
The drain regions of the driver transistors D
1
and D
2
are connected to the source/drain regions on one side of the access transistors A
1
and A
2
respectively. The source regions of the driver transistors D
1
and D
2
are connected to ground (VEE line). The gate electrode of the driver transistor D
1
is connected to the source/drain region of the access transistor A
2
, and the gate electrode of the driver transistor D
2
is coupled to the source/drain region of the access transistor A
1
. The source/drain regions on one side of the load transistors P
1
and P
2
are connected to the source/drain regions on one side of the access transistors A
1
and A
2
. The source/drain regions on the other side of the load transistors P
1
and P
2
are connected to power supply line (VCC line).
For a data write operation, the word line (WL) is selected so as to turn on the access transistors A
1
and A
2
. A voltage is then forced onto the bit line pair in accordance with a desired logical value, whereby the flip-flop circuit has its bi-stable state brought into one of the two settings described above.
For a data read operation, the access transistors A
1
and A
2
are first turned on. Then a potential on the memory nodes N
1
and N
2
is transmitted to the bit lines.
Having the above-described constitution, so-called six-transistor type SRAM cells that use PMOSs as load transistors formed on a substrate are extensively practiced today (called full-CMOS type SRAM cells hereunder). In a full-CMOS type SRAM cell, the drain region (P
+
diffusion region) of the PMOSs (load transistors) constituting one inverter of the flip-flop circuit needs to be connected to the drain region (N
+
diffusion region) of the NMOSs (driver transistors).
Traditionally, full-CMOS type SRAM cells utilize metal lead providing ohmic contacts for interconnection, i.e., local lead that encompasses all lead arrangements connecting diffusion layers of transistors as well as contiguous elements. Illustratively, Japanese Patent Laid-Open No. Hei 9-55440 discloses a full-CMOS type SRAM that uses metal arrangements for lead. The disclosed semiconductor device has tungsten-embedded electrodes connecting metal lead layers to the substrate, and also has tungsten-embedded electrodes connecting contact holes that link contiguous elements.
Generally, metal lead has poor workability. Pattern pitches can be reduced to only a certain extent, so that it is difficult to achieve further miniaturization. Another disadvantage of metal lead-in general is its poor resistance to heat. This limits the scope of thermal treatment following pattern formation.
One proposed solution to the above difficulties with conventional full-CMOS type SRAM cells involves the use of a polycrystal silicon film as lead that connects specifically the drain regions of PMOSs (load transistors) to those of NMOSs (driver transistors). However, the use of such a polycrystal silicon film in the conventional SRAM poses other problems, as will be described below.
FIGS. 33 and 34
are an equivalent circuit diagram and a cross-sectional view of the conventional SRAM respectively, both intended to explain problems therewith. In
FIG. 34
, reference numeral
51
is an N
−
-type silicon substrate,
52
is a P-type well region,
53
is an N-type well region, and
54
is a field insulating film for isolating elements. Driver transistors are formed on the surface of the P-type well region
52
surrounded by the field insulating film
54
. Each driver transistor is composed of N
+
-type source/drain regions
55
a
and
55
b,
N
−
-type source/drain regions
56
a
through
56
c,
a gate oxide film
58
, a gate electrode
59
a,
and a side wall oxide film
60
.
Load transistors are formed on the surface of the N-type well region
53
surrounded by the field insulating film
54
. Each load transistor is made up of a P
+
-type source/drain region
57
, a gate oxide film
58
, a gate electrode
59
b,
and a side wall oxide film
60
. The entire surface is covered with a silicon dioxide film
61
. Contact holes
62
a
and
62
b
are formed on the N
+
-type source/drain region
55
b
of the driver transistor and on the P
+
-type source/drain region
57
of the load transistor. A polycrystal silicon film
63
is formed inside the contact holes
62
a
and
62
b
as well as over the silicon dioxide film
61
. The polycrystal silicon film
63
is a P-type polycrystal silicon film doped with P-type impurities such as boron. The P-type polycrystal silicon film connects the N
+
-type source/drain region
55
b
of the driver transistor to the P
+
-type source/drain region
57
of the load transistor.
It should be noted that transistor-to-transistor connection by means of single-layer lead leads to connecting the drain regions of PMOSs (load transistors) to those of NMOSs (driver transistors) through a conductive polycrystal silicon film. In the interconnection utilizing a single-layer polycrystal silicon film of the same conductivity, as shown in
FIGS. 33 and 34
, subsequent heat treatment causes the polycrystal silicon film to diffuse impurities into the silicon substrate. This leads to another problem: PN diodes are formed in the silicon substrate.
The PN diodes are produced because P-type impurities contained in the polycrystal silicon film
63
are diffused into the substrate, thereby generating a P
+
-type diffusion region
64
in the N
+
-type source/drain region
55
b.
This allows the High level of the memory nodes N
1
and N
2
to rise just up to VCC-Vbi (Vbi: built-in potential of PN junction≈0.8 V), which tends to make the High level of the memory nodes unstable. With the High node level in such an unstable state, a drop in the resistance to so-called soft errors may become pronounced.
Soft errors can occur as follows: alpha rays upon entry from the outside such as the package material produce electron-hole pairs. Of these pairs, electrons are attracted to memory nodes in the memory cells and invert stored data in the cells, causing random errors called soft errors. When the High node level of the memory cells drops dragged by a falling potential accumulated therein, the resistance to such soft errors will deteriorate.
When the polycrystal silicon
Bowers Charles
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thompson Craig
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