Method of fabricating metal oxide semiconductor

Details Method of fabricating metal oxide semiconductor Method of fabricating metal oxide semiconductor

1998-12-15

2001-01-16

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000

Reexamination Certificate

active

06174778

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a fabricating method of metal oxide semiconductor.
2. Description of the Related Art
As integrated circuits become more complicated and their function becomes more powerful, required density of transistors in an integrated circuit increases correspondingly. The high density of these complex integrated circuits cannot be easily achieved by simply decreasing a layout according to device proportions of the integrated circuits. The device size must be decreased by a design rule and with consideration for possible change in the physical characteristics of the device. For example, channel length of a metal oxide semiconductor (MOS) transistor cannot be educed infinitely. Reduction size may cause a short channel effect. Once the short channel effect happens, a punch through problem is likely to occur. The punch through problem occurs due to current leakage when the MOS transistor is switched off. The conventional solution to the punchthrough problem is to increase punchthrough voltage, in a procedure such as a punchthrough stopper implantation or a halo implantation.
FIG.
1
and
FIG. 2
respectively explain the related positions of an anti-punchthrough region and a metal oxide semiconductor formed by a conventional method.
In
FIG. 1
, an N-type MOS field effect transistor (NMOSFET) is taken as an example. In a typical punchthrough stopper implantation, p-type impurities are implanted in the substrate
100
before forming a gate
106
and a source/drain region
120
. A heavily doped anti-punchthrough region
114
is formed in the substrate
100
below the surface-channel region
112
between the source/drain region
120
.
In
FIG. 2
, a tilt-angle halo implantation step is performed after a gate
206
and a source/drain extension
210
a
are formed. P-type impurities are locally implanted in the substrate
200
. An anti-punchthrough region
214
, which is connected to the source/drain extension
210
a,
is formed in the substrate
300
. In contrast with the anti-punchthrough region
114
formed by punchthrough stopper implantation, the anti-punchthrough region
214
formed by halo implantation, which region connects to the extension region
210
a,
has higher anti-punchthrough ability. Hence, the anti-punchthrough region
214
is more suitable than the anti-punchthrough region
114
for a MOS occupying a small planar area.
But difficulty is still encountered when trying to resolve the punchthrough problem. In the conventional MOS transistor as shown in
FIG. 2
, phosphorus (P) ions and arsenic (As) ions are often implanted in the substrate
200
to form the anti-punchthrough region
214
. Light ions, such as P ions and As ions, with high diffusion coefficients, easily diffuse to the source/drain region
220
in the following thermal step. When the ions of anti-punchthrough region
214
diffuse to the source/drain region
220
, the ion concentration of the anti-punchthrough region
214
is decreased, so the punchthrough problem is not effectively resolved. In order to increase the anti-punchthrough ability of the device, the punchthrough voltage must be increased. The conventional method for increasing the anti-punchthrough voltage of the device is to increase the concentration of the anti-punchthrough region
214
. However, as the concentration of anti-punchthrough region
214
increases, the intensity of a body effect increases. In this manner, the voltage applied to the device must be increased in order to operate the device. In addition, as the concentration of the anti-punchthrough region
214
increases, the junction capacitance increases, which reduces the performance of the device.
SUMMARY OF THE INVENTION
One aspect of the invention is to provide an improved fabricating method for a metal oxide semiconductor, which is suitable for a highly integrated device.
Another aspect of the invention is to provide a fabricating method for a metal oxide semiconductor, which decreases the possibility of punchthrough problems arising from short channel effects.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a metal oxide semiconductor. The invention includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate. A spacer is formed on a sidewall of the gate. A source/drain region is formed in the substrate beside the spacer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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patent: 5593907 (1997-01-01), Anjum
patent: 5753556 (1998-05-01), Katada et al.
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patent: 5970353 (1999-10-01), Sultan
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S.Wolf Silicon Processing for The VSLI Era Lattice press v.3 p. 238-242,290,309-311, 621-622, 1995.

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