Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-19
2001-06-12
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000
Reexamination Certificate
active
06245614
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a split-gate flash memory cell. More particularly, the invention relates to a method of manufacturing a self-aligned split-gate flash memory cell with an improved coupling ratio.
2. Description of the Prior Art
EEPROM (electrically erasable programmable read only memory) is a very popular memory device used in the electronics industry because it can store data in a non-volatile manner for more than 10 years, and it can be reprogrammed or erased many times. But one weakness of EEPROM devices is that their memory access time is quite slow compared to other memory devices. In order to solve this problem, a flash EEPROM device was developed by Intel. In contrast to traditional EEPROM, the flash EEPROM can erase recorded data a block at a time instead of a byte at a time, and thus dramatically increases the memory access time.
The flash memory technology achieves high density due to a smaller memory cell size realized in a stacked-gate memory cell profile. A stacked-gate flash memory cell comprises a floating gate for storing electric charge, a control gate for controlling the charging of the floating gate, and a dielectric layer positioned between the floating gate and the control gate. Like a capacitor, the flash memory stores electric charge in the floating gate to represent a digital data bit of “1”, and removes charge from the floating gate to represent a digital data bit of “0”.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional diagram of a conventional stacked-gate flash memory cell
10
. As shown in
FIG. 1
, the stacked-gate flash memory cell
10
comprises a stacked-gate
11
, a drain
22
and a source
24
. The drain
22
and the source
24
define the channel length in the silicon substrate
20
under the stacked-gate
11
. The stacked-gate
11
comprises a gate oxide layer
12
, a floating gate
14
stacked on the gate oxide layer
12
, an insulating layer
16
stacked on the floating gate
14
, and a control gate
18
stacked on the insulating layer
16
. By virtue of tunneling effects, hot electrons are injected into the floating gate
14
from the drain
22
through the gate oxide layer
12
so as to change the threshold voltage of the floating gate
14
and thus enable the storage of data. Although the stacked-gate flash memory cell
10
enhances integration, it is, however, prone to over-erasing.
Please refer to FIG.
2
.
FIG. 2
is a cross-sectional diagram of a conventional split-gate flash memory cell
30
. As shown in
FIG. 2
, the split-gate flash memory cell
30
comprises a gate oxide layer
32
, a floating gate
34
, a control gate
38
, a drain
42
and a source
44
. Similarly, the floating gate
34
and control gate
38
are separated by an insulating layer
36
. Portions of the control gate
38
overlay the floating gate
34
, and the remaining portions of the control gate
38
directly overlay the channel
31
. The split-gate flash memory cell
30
is superior to the stacked-gate flash memory cell
10
in terms of cell reliability, yet occurrences of unstable channel current due to variations of the stepper system are often observed. This unstable channel current results from misalignment of the overlapping area between the control gate
38
and floating gate
34
. Furthermore, the coupling ratio of the conventional split-gate flash memory cell is insufficient, leading to a reduced erasing rate and inferior product endurance.
Please refer to FIG.
3
.
FIG. 3
illustrates an equivalent circuit
46
of the conventional split-gate flash memory cell
30
depicted in FIG.
2
. As shown in
FIG. 3
, C
1
is the capacitance between the floating gate
34
and the control gate
38
, C
2
is the capacitance between the floating gate
34
and the source
44
, C
3
is the capacitance between the floating gate
34
and the silicon substrate
40
, and C
4
is the capacitance between the floating gate
34
and the drain
42
. The coupling ratio (CR value) of the split-gate flash memory cell
30
is defined as:
CR=C
1
/(C
1
+C
2
+C
3
+C
4
)
CR value is an index that is usually used to evaluate the performance of a split-gate flash memory cell. The higher the coupling ratio, the better the performance of the flash memory cell. According to the above equation, one approach to increase the CR value is to increase the capacitive surface between the floating gate
34
and the control gate
38
, as this surface is proportional to the capacitance C
1
. On the other hand, increasing the CR value can also be achieved by decreasing the capacitive surface between the floating gate
34
and the silicon substrate
40
,as this surface is proportional to C
3
.
Please refer to
FIG. 4
to FIG.
7
.
FIG. 4
to
FIG. 7
are cross-sectional diagrams of forming a split-gate flash memory cell
80
on a semiconductor wafer
50
according to the prior art method. As shown in
FIG. 4
, the semiconductor wafer
50
comprises a silicon substrate
52
and a silicon oxide layer
54
positioned on the silicon substrate
52
.
As shown in
FIG. 5
, a patterned photo-resist layer
56
is first formed on the surface of the silicon oxide layer
54
. An ion implantation process is then performed to form two doped regions on the surface of the silicon substrate
52
. The photo-resist layer
16
serves as a hard mask during the ion implantation process. A rapid thermal processing (RTP) is used to drive the dopants into the silicon substrate
52
so as to form two diffused regions
62
, which serve as a source and a drain of the split-gate flash memory cell
80
.
As shown in
FIG. 6
, the photo-resist layer
56
is completely removed and a low-pressure chemical vapor deposition (LPCVD) process is performed to form a polysilicon layer (not shown). A patterned photo-resist layer
66
is formed on the surface of the polysilicon layer. An anisotropic etching process is then performed using the photo-resist layer
66
as a hard mask to vertically remove the polysilicon layer down to the surface of the silicon oxide layer
54
so as to form a floating gate
64
.
Finally, as shown in
FIG. 7
, the photo-resist layer
66
is removed and an LPCVD process is performed to form a silicon oxide layer
68
on the surface of the semiconductor wafer
50
. The silicon oxide layer
68
serves as a tunnel oxide layer of the split-gate flash memory cell
80
. Another LPCVD process is then performed to form a polysilicon layer (not shown) on the surface of the silicon oxide layer
68
and a patterned photo-resist layer is formed on the polysilicon layer. An anisotropic etching process is then performed using the photo-resist layer as a hard mask to vertically remove the polysilicon layer down to the surface of the silicon oxide layer
68
so as to form the control gate
70
.
SUMMARY OF THE INVENTION
It is a primary objective of the present invention to provide a method of fabricating a self-aligned split-gate flash memory cell with a superior coupling ratio, and to provide a manufacturing process that can effectively enhance the performance of split-gate flash memory products.
In accordance with the objective of the invention a new method of fabricating a high coupling ratio split-gate flash memory cell is disclosed. A semiconductor wafer is first provided having a substrate, at least two select gates formed on the substrate, and a dielectric layer formed on each select gate. A polysilicon spacer acting as a floating gate is formed on each of the inner walls between the two select gates. A drain is formed in the substrate adjacent to each of the outer walls of the two select gates. A source is formed in the substrate between the two polysilicon spacers by using a self-aligned ion implantation process. A silicon oxide layer is provided on the surface of the semiconductor wafer to cover the dielectric layer, the select gates and the polysilicon spacers. A dry etching process is used to remove a predetermined thickness of the silicon oxide layer and to remove the dielectric layer above
Chaudhari Chandra
Hsu Winston
United Microelectronics Corp.
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