Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-15
2001-03-13
Carroll, J. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S250000, C438S251000, C438S254000, C438S393000, C438S397000
Reexamination Certificate
active
06200846
ABSTRACT:
This application is based on Japanese Patent Application No. 10-106623 filed on Apr. 16, 1998, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device formed with MISFETs and capacitors and its manufacture method.
b) Description of the Related Art
A conventional method of manufacturing a semiconductor device having capacitors and MISFETs will be described with reference to
FIGS. 5A
to
5
C and
FIGS. 6A and 6B
.
As shown in
FIG. 5A
, an n-type well
102
is formed in a partial region of a surface layer of a p-type silicon substrate
100
. A field oxide film
101
is formed on the surface of the silicon substrate
100
to define the region where the n-type well
102
was formed and an active region in the p-type surface layer of the silicon substrate
100
. The surface layer in the active region is thermally oxidized to form a gate insulating film.
A first polysilicon film
103
is deposited on the field oxide film
101
, this film
103
being doped with impurities to impart an n-type conductivity. A capacitor dielectric film
104
made of SiO
2
is deposited on the first polysilicon film
103
. A second polysilicon layer
105
is deposited on the capacitor dielectric film
104
, this film
105
being doped with impurities to impart the n-type conductivity.
Of the surface of the second polysilicon film
105
, a partial area above the field oxide film
101
is covered with a resist pattern
110
. By using the resist pattern
110
as a mask, the second polysilicon film
105
is etched. Thereafter, the resist pattern
110
is removed.
As shown in
FIG. 5B
, an upper electrode
105
a
made of the second polysilicon film
105
is being left.
As shown in
FIG. 5C
, an SiN film
106
is deposited on the capacitor dielectric film
104
and upper electrode
105
a.
Of the surface of the SiN film
106
, a partial area inclusive of the area above the upper electrode
105
a
is covered with a resist pattern
111
. By using the resist pattern
111
as a mask, the SiN film
106
and capacitor dielectric film
104
are etched. Thereafter, the resist pattern
111
is removed.
As shown in
FIG. 6A
, an SiN film
106
covering the upper electrode
105
a
and a capacitor dielectric film
104
a
under the SiN film
106
are being left. Of the surface of the first polysilicon film
103
, the areas where gate electrodes are to be formed are covered with resist patterns
108
. By using the resist patterns
108
and SiN film
106
a
as a mask, the first polysilicon film
103
is etched. Thereafter, the resist patterns
108
are removed.
As shown in
FIG. 6B
, gate electrodes
103
b
and
103
c
are being left on the gate insulating film on the active regions. A lower electrode
103
a
made of the first polysilicon film
103
is being left under the SiN film
106
a.
With the above processes, a capacitor
109
is formed having the lower electrode
103
a,
capacitor dielectric film
104
a,
and upper electrode
105
a.
A p-channel MISFET and an n-channel MISFET are formed respectively in the n-type well
102
and p-type active region through ordinary MISFET manufacture processes.
With the method described with reference to
FIGS. 5A
to
5
C and
FIGS. 6A and 6B
, two photolithography processes are required to form the capacitor
109
, by using the resist pattern
110
for the upper electrode shown in FIG.
5
A and the resist pattern
111
for the lower electrode shown in FIG.
5
C. These two photolithography processes are required in addition to the MISFET manufacture processes.
Another method proposed heretofore forms the capacitor lower electrode and gate electrode by one photolithography process after the upper electrode and capacitor dielectric film
104
are formed through selective etching using the resist pattern
110
shown in FIG.
5
A. With this method, the capacitor can be formed by adding one photolithography process. However, the side wall of the upper electrode of the capacitor and the upper surface of the lower electrode are separated only via the side wall of the capacitor dielectric film. A lowered breakdown voltage or an increased leak current of the capacitor become easy to occur.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacture method capable of suppressing an increase in the number of photolithography processes and forming a capacitor of high reliability.
It is an object of the present invention to provide a semiconductor device capable of suppressing an increase in the number of photolithography processes and forming a capacitor of high reliability.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: depositing a first silicon film on a semiconductor substrate exposing insulating material on a partial surface of the semiconductor substrate; forming a capacitor dielectric film on the first silicon film; forming a second silicon film on the capacitor dielectric film; patterning the second silicon film to leave an upper electrode made of the second silicon film above the partial surface exposing the insulating material; depositing a first insulating film on the upper electrode and the capacitor dielectric film; anisotropically etching a lamination structure of the first insulating film and the capacitor dielectric film, to leave a spacer insulating film made of the first insulating film on side walls of the upper electrode and to leave a portion of the capacitor dielectric film under the upper electrode and the spacer insulating film; and patterning the first silicon film to leave a lower electrode made of the first silicon film in an area inclusive of the upper electrode and the spacer insulating film.
When the capacitor dielectric film is anisotropically etched, the upper surface of the upper electrode and the upper surface of the first silicon film are separated by the side wall surface of the first spacer insulating film. Leak current between the upper electrode and the first silicon film can therefore be suppressed. The first silicon film under the capacitor dielectric film is a capacitor lower electrode. Leak current between the upper and lower electrodes can be prevented from being increased.
The first and second silicon films may be other conductive films not using silicon.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having an insulating surface; a lower electrode disposed on a partial area of the insulating surface of the semiconductor substrate; a capacitor dielectric film disposed on a partial area of an upper surface of the lower electrode and made of high dielectric material or paraelectric material; an upper electrode disposed in a partial area of an upper surface of the capacitor dielectric film; and a spacer insulating film made of a same material as the capacitor dielectric film, the spacer insulating film covering the upper surface of the capacitor dielectric film not covered with the upper electrode and side walls of the upper electrode.
The upper surface of the upper electrode is separated from the upper surface of the lower electrode by the side wall surface of the spacer insulating film. Leak current between the upper and lower electrodes can therefore be suppressed.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming element isolation structures on a surface of a semiconductor substrate to define active regions for MISFETs; forming a gate insulating film on surfaces of the active regions; depositing a first conductive film on the element isolation structures and the gate insulating film; forming a capacitor dielectric film on the first conductive film; depositing a second conductive film on the capacitor dielectric film; patte
Armstrong Westerman Hattori McLeland & Naughton LLP
Carroll J.
Fujitsu Limited
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