Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-21
2001-08-14
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06274438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a contact programmable ROM having a new structure and a method of manufacturing the same. The contact programmable ROM refers to a ROM (read only memory) in which whether a contact hole is electrically connected to an interconnecting layer or not corresponds to whether information exists or not.
2. Description of Related Art
ROM is a type of nonvolatile memory cell. The structure of memory cell of a mask ROM does not require any special semiconductor device manufacturing process in manufacturing, therefore mask ROM is advantageous in process economy, and no requirement of writing operation allows a simplified circuit structure as a whole, therefore it is advantageous for realizing of large-capacity memory. However, mask ROM is disadvantageous due to long turn around time (time for delivery from a semiconductor manufacturer to a user) comparing with EPROM. Diffusion layer programming, ion implantation, and contact programming are types of ROM manufacturing process, among these processes, contact programming is a process in which a programming process is provided near the final process of semiconductor device manufacturing process, the contact programming system is a process which can realize the shortest TAT.
A plane view and an equivalent circuit of a contact programmable ROM which are formed when projected on a plane are shown in
FIGS. 6A and 6B
. In a contact programmable ROM, information is stored in a memory depending on whether one source/drain region is connected to bit lines or not. That is, in a situation that one source/drain region is connected to a bit line, when a transistor of a memory cell is turned on, charge on a bit line discharges to read a “0” level information. On the other hand, in a situation that one source/drain region is not connected to a bit line, when a transistor of a memory cell is turned on, charge on a bit line is held to read a “1” level information. Another source/drain region of each memory is connected to common Vss (GND).
The outline of a manufacturing process of conventional contact programmable ROM is described referring to schematic fragmentary sectional views of semiconductor substrate shown in
FIGS. 3A
,
3
B,
4
A, and
4
B. In addition, a flow chart for illustrating conventional contact programmable ROM manufacturing process is shown in FIG.
5
.
Process-
10
First, a memory cell is manufactured prior to programming process. On a semiconductor substrate
10
, a plurality of memory cells comprising a gate region
14
and source/drain regions
15
A and
15
B are formed. To form the plurality of memory cells, an element separation region
11
is formed on the semiconductor substrate
10
, subsequently, a gate oxide film
12
comprising SiO
2
is formed on the surface of the semiconductor substrate. Then, a polysilicon layer
13
is formed over the whole surface, the polysilicon layer
13
is patterned to form a gate region
14
comprising a gate oxide film
12
and polysilicon layer
13
. Next, on the region where source/drain regions are to be formed, an impurity is injected by ion implantation technique, the injected impurity is activated to form source/drain region
15
A and
15
B. As described herein above, source/drain regions
15
A and
15
B are formed.
FIG. 3
shows two drain regions
15
A and
15
B of two memory cells, and the drain region
15
B is common to both the memory cells. Usually, BPSG is used as an interlayer insulating layer, but BPSG is deteriorated with time significantly. Memory cells are stored for relatively long time before programming process, therefore, usually an insulating film
16
is formed over the whole surface (refer to
FIG. 3A
) without forming an interlayer insulating layer.
When a program is assigned and various photomask are completed, the manufacturing of contact programmable ROM restarts. TAT in the manufacturing of conventional contact programmable ROM starts at the time.
Process-
20
First, an interlayer insulating layer
30
comprising BPSG is formed over the whole surface. Then, an opening
31
is formed on the interlayer insulating layer
30
above the one source/drain region
15
A of a specified memory cell (refer to FIG.
3
B). In the conventional contact programmable ROM, one source/drain region
15
A of a memory cell which is to hold “0” level information is connected to a bit line. On the other hand, one source/drain region
15
A of a memory cell which is to hold “1” level information is not connected to a bit line. Therefore, a specified memory cell herein refers to a memory cell which is to hold “0” level information.
Process-
30
With recent progress of minimization, the diameter of contact hole becomes smaller. Therefore, a technique to fill consistently the internal of an opening, which is provided on the interlayer insulating layer, with metal interconnect material is the very important technical subject. Blanket tungsten CVD is one of the methods for consistent filling. In this method, tungsten is deposited by thermal CVD on the interlayer insulating layer
30
including the internal of the opening
31
. Next, the tungsten deposited on the interlayer insulating layer
30
is removed selectively by etching back technique. Thereby, a metal interconnect material
32
comprising tungsten is filled in the opening
31
and a contact hole is completed (refer to FIG.
4
A).
Process-
40
Then, on the contact hole and interlayer insulating layer
30
, for example, aluminum alloy is deposited by spattering, and the aluminum alloy layer is patterned by photolithographing and dry etching to form an interconnecting layer (refer to FIG.
4
B).
In a contact programmable ROM, a gate region
14
of each memory cell is connected electrically to gate regions
14
of adjacent memory cells to form a word line. In
FIG. 4
, the gate region
14
is connected to gate regions of adjacent memory cells located in the perpendicular direction to the paper plane. More in detail, gate regions
14
are integrated by connecting a plurality of memory cells. Another source/drain region
15
B of each memory cell is connected electrically to another source/drain regions
15
B of adjacent memory cells. In
FIG. 4
, another source/drain region
15
B is connected electrically to another source/drain regions of adjacent memory cells located in the perpendicular direction to the paper plane. More in detail, another source/drain regions
15
B are integrated by connecting a plurality of memory cells. Another source/drain regions
15
B are connected to Vss (GND), and the interconnecting layer
33
is equivalent to a bit line.
In the conventional manufacturing of contact programmable ROM, TAT starts from forming of contact hole described in the Process-
20
. As described in the Process-
20
, filling of opening with metal interconnect material (forming of contact hole, Process-
20
), which is relatively difficult process) is included in the process which relates directly to TAT of contact programmable ROM, the inclusion prevents TAT from shortening. In addition, because the number of openings to be provided should be changed depending on the program, it is difficult to stabilize the forming of contact holes.
Accordingly, the object of the present invention is to provide a method for manufacturing contact programmable ROM in which TAT is shortened and a contact hole is formed stably, and to provide a contact programmable ROM manufactured by this manufacturing method.
SUMMARY OF THE INVENTION
The object of the present invention is accomplished by providing a method for manufacturing contact programmable ROM in which whether a contact hole is connected electrically to an interconnecting layer or not corresponds to whether information exists or not, comprising the steps of:
(a) the first step in which a plurality of memory cells comprising gate region and source/drain region are formed on a semiconductor substrate, then, the first interlayer insulating layer is formed over the whole surface, the first opening is formed on the first interlayer in
Sonnenschein Nath & Rosenthal
Sony Corporation
Tsai Jey
LandOfFree
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