Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-07
2001-09-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S637000, C438S675000
Reexamination Certificate
active
06287951
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a process for forming a semiconductor device, and more particularly, to methods for forming semiconductor device interconnects.
RELATED ART
Reducing semiconductor device feature geometries is becoming increasingly important in order to reduce the size and increase the speed of integrated circuits. Inlaid interconnect trenches and contacts are examples of such features. Inlaid interconnect trenches are typically used to form the metallization levels of an integrated circuit, and inlaid contacts are used to provide electrical connections between the various metallization levels.
During the formation of the interconnect trench and contact openings, it is desirable to maintain consistent and reproducible dimensions between the top and bottom portions of the opening. However, conventional patterning and etching techniques often result in undesirable patterning variations and slope of the etched features. For example, resist is typically eroded during the etch process that defines the feature opening. Depending on the etch time, etch chemistry, and the resist thickness, the resist erosion translates to varying degrees of erosion of the etched feature. The erosion produces sloping sidewalls that can be nonuniformly distributed across the wafer.
Increasing the thickness of the resist can reduce erosion-related problems, however, this requires increasing the resist exposure time, and reduces throughput. In addition, increasing the thickness of the resist negatively impacts the lithography process because it increases the depth of focus requirements during the exposure processing step. Also, increasing the thickness of the resist complicates the etching process because it further increases the aspect ratio of the feature being etched.
Another source of patterning variation includes the reflection from underlying topography. This reflected radiation, in effect, increases the radiation dose of the resist in areas where reflections are more prevalent. This can increase the size of, or distort, the resist feature opening. Underlying films having higher reflectivity and non-planar surfaces are more prone to produce problems with reflected radiation. Problems associated with reflectivity typically increase as the number of interconnect levels and the density of features in the underlying topography increase.
The prior art has shown that depositing approximately 60 to 140 nanometers of silicon oxynitride, prior to forming and patterning the resist layer, reduces reflectivity problems associated with underlying topography. However, this also makes it necessary to increase the thickness of the resist layer to accommodate etching through the added film. In addition, the combination of the added antireflective layer and the thicker resist contribute to an increase in the overall aspect ratio of the feature during etching, which increases the difficulty of etching it.
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Clark Wayne D.
Filipiak Stanley M.
Lii Yeong Jyh
Lucas Kevin D.
Pettinato Christopher D.
Bowers Charles
Motorola Inc.
Rodriguez Robert A.
Smoot Stephen W.
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