Semiconductor device with silicide layers and fabrication...

Details Semiconductor device with silicide layers and fabrication... Semiconductor device with silicide layers and fabrication...

1999-03-02

2001-09-11

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S238000, C438S258000, C257S326000

Reexamination Certificate

active

06287911

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with silicide layers and a fabrication method thereof and more particularly, to a semiconductor device equipped with at least two sections necessitating different electric characteristics or performance of built-in electronic elements/circuits, such as a logic circuit section, a Dynamic Random-Access-Memory (DRAM) cell section, a peripheral or control circuit section of DRAM cells, and so on, and a fabrication method of the device.
2. Description of the Prior Art
Conventionally, a semiconductor device equipped with a logic circuit section including logic circuits such as sensing amplifiers and a DRAM cell section including an array of DRAM cells is known, which has been practically used in various application fields. Not only the logic circuits but also the DRAM cells are typically formed by Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).
In the semiconductor devices of this sort, to increase the operation speed of the logic circuits provided in the logic circuit section, silicide layers of a refractory metal such as tungsten (W), titanium (Ti), molybdenum (Mo), cobalt (Co), and nickel (Ni) need to be incorporated into source/drain regions and gate electrodes of MOSFETs that constitute the logic circuits. This is because the refractory-metal silicide layers are lower in electric resistance than single-crystal silicon (Si) and polysilicon layers.
Typically, the refractory-metal silicide layers are produced by a chemical reaction of a refractory metal with Si during a heat treatment process, which is termed a “silicidation reaction”. Therefore, not only the logic circuit section but also the DRAM cell section, which are located on a same silicon substrate, are subjected to the heat treatment process. Thus, the refractory-metal silicide layers are incorporated in the source/drain regions and the gate electrodes of the MOSFETs in both the logic circuit section and the DRAM cell section.
The refractory-metal silicide layers incorporated in the source/drain regions in the DRAM cell section tend to increase the current leakage at the p-n junctions of the relating source/drain regions. Therefore, there arises a problem that the data-storing characteristic or performance of the DRAM cells is degraded.
To solve this problem, a configuration shown in
FIG. 1
may be thought. In this configuration, a patterned isolation dielectric
119
is formed on a main surface of a p-type single-crystal Si substrate
101
, thereby defining a logic circuit section
120
having n-channel MOSFETs
121
and a DRAM cell section
130
having n-channel MOSFETs
131
and storage capacitors
132
. For the sake of simplification of description, one of the MOSFETs
121
, one of the MOSFETs
131
, and one of the capacitors
132
are shown in
FIG. 1
, and explanation about only these three elements is presented below.
In the logic circuit section
120
, a pair of n
+
-type diffusion regions
109
b
and a pair of n
−
-type diffusion regions
110
b
are formed in the substrate
101
, thereby forming a pair of source/drain regions
104
b
and
105
b
with the Lightly-Doped Drain (LDD) structure. One of the two diffusion regions
109
b
located at the right-hand side and the adjoining diffusion region
110
b
form the source/drain region
104
b
. The other of the two diffusion regions
109
b
located at the left-hand side and the adjoining diffusion region
110
b
form the source/drain region
105
b.
A gate insulating layer
102
b
is formed on the main surface of the substrate
101
between the pair of n
+
-type diffusion regions
109
b
. The gate insulating layer
102
b
is overlapped with the underlying pair of n
−
-type diffusion regions
110
b
. A polysilicon layer
103
b
and a pair of sidewall spacers
114
b
are formed on the gate insulating layer
102
b
. The pair of sidewall spacers
114
b
are located at each side of the polysilicon layer
103
b
. Further, a sulicide layer
112
b
of a refractory metal is formed on the polysilicon layer
103
b
to be sandwiched by the sidewall spacers
114
b
. The silicide layer
112
b
and the polysilicon layer
103
b
serves as a gate electrode
118
b.
The pair of source/drain regions
104
b
and
105
b
, the gate insulating layer
102
b
, the gate electrode
118
b
, and the pair of sidewall spacers
114
b
constitute the MOSFET
121
.
In the DRAM cell section
130
, a pair of n
+
-type diffusion regions
109
a
and a pair of n
−
-type diffusion regions
110
a
are formed in the substrate
101
, thereby forming a pair of source/drain regions
104
a
and
105
a
with the LDD structure. One of the two diffusion regions
109
a
located at the right-hand side and the adjoining diffusion region
110
a
form the source/drain region
104
a
. The other of the two diffusion regions
109
a
located at the left-hand side and the adjoining diffusion region
110
a
form the source/drain region
105
a.
A gate insulating layer
102
a
is formed on the main surface of the substrate
101
between the pair of n
+
-type diffusion regions
109
a
. The gate insulating layer
102
a
is overlapped with the underlying pair of n
−
-type diffusion regions
110
a
. A polysilicon layer
103
a
and a pair of sidewall spacers
114
a
are formed on the gate insulating layer
102
a
. The pair of sidewall spacers
114
a
are located at each side of the polysilicon layer
103
b
. Further, a silicide layer
112
a
of a refractory metal is formed on the polysilicon layer
103
a
. The silicide layer
112
a
and the polysilicon layer
103
a
serves as a gate electrode
118
a.
The pair of source/drain regions
104
a
and
105
a
, the gate insulating layer
102
a
, the gate electrode
118
a
, and the pair of sidewall spacers
114
a
constitute the MOSFET
131
.
Further, an n-type diffusion region
108
is formed in the substrate
101
to be contacted with the n
+
-type diffusion region
109
a
located at the right-hand side and the isolation dielectric
119
. The diffusion region
108
serves as a lower electrode of the capacitor
132
. A capacitor dielectric layer
107
is selectively formed on the diffusion region
108
. A conductive layer
106
is selectively formed on the isolation dielectric
119
to be contacted with the capacitor dielectric layer
107
. The conductive layer
106
serves as an upper electrode of the capacitor
132
.
The capacitor
132
is electrically connected to the MOSFET
131
at the contact area of the diffusion regions
108
and
109
a.
With the device configuration shown in
FIG. 1
, since no silicide layer is incorporated in the source/drain regions
104
a
and
105
a
of the MOSFET
131
in the DRAM cell section
130
, the above-described problem that the data-storing characteristic or performance of the DRAM cells is degraded can be solved. However, in this case, there arises anther problem that the operation speed of the logic circuits (i.e., the MOSFET
121
) in the logic circuit section
120
is not satisfactorily high.
Thus, it is necessary to develop a technique enabling the selective silicidation reaction of the source/drain regions in the logic circuit section
120
and the DRAM cell section
130
.
An example of the selective silicidation technique is shown in
FIGS. 2A
to
2
C, which is substantially the same as that disclosed in the Japanese Non-Examined Patent Publication No. 1-264257 published in October 1989.
In the conventional selective silicidation technique disclosed in the Japanese Non-Examined Patent Publication No. 1-264257, as shown in
FIG. 2C
, a patterned isolation dielectric
219
is formed on a main surface of a p-type single-crystal Si substrate
201
, thereby defining a logic circuit section
220
having an n-channel MOSFET
221
and a DRAM cell section
230
having an n-channel MOSFET
231
and a storage capacitor
232
.
In the logic circuit section
220
, a pair of n
+
-type diffusion regions
209
b
and a pair of n
−
-type diffusion regions
210
b
are formed i

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