Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-10-28
2001-01-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S158000, C365S171000, C365S173000
Reexamination Certificate
active
06175525
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the field of electronic memory devices, and more particularly, to non-volatile memory devices that can assume a desired state when power is applied.
Most digital electronic devices use both logic gates and memory elements to implement a desired function. The memory elements are used to store initial, intermediate and/or final data. The logic gates are used to provide and/or receive the data to/from the memory elements, and perform the necessary data manipulation. In a typical digital system, the basic memory elements are bi-stable logic circuits known as latching elements. There are numerous types of latching elements including, for example, D-latches, RS-latches, JK-latches, etc. These latching elements are often combined to form various forms of flip-flops or other storage devices.
Latching elements typically use one or more feedback paths that have an even number of inversions. By providing an even number of inversions, the feedback path reinforces the data state of the latching element. To write a desired state to the latching element, the feedback path is typically overdriven or a switch is provided to temporarily interrupt the feedback path while a new data state is provided to the latching element. The most basic latching element includes a pair of cross-coupled inverters. There are, however, numerous other known implementations.
A limitation of many conventional latching elements is that the data stored therein is lost when power is lost or otherwise interrupted. For example, when a personal computer or other data processing system loses power, the data stored in the latching elements are lost. When power is restored, the data processing system assumes a state that is unrelated to the state of the data processing system before the power loss. Often, much of the processing that was completed coincident with or prior to the power loss is lost, or must be re-constructed and/or re-executed which can be a time consuming and tedious task.
In high reliability applications, a primary power source and an auxiliary power source may be provided to reduce the likelihood that the latching elements will experience a power loss. In such systems, an auxiliary power source is used when the primary power fails. A limitation of this approach is that significant overhead is required including an auxiliary power source, a power degradation detection mechanism and a power switching mechanism. In addition, the auxiliary power source is often a battery or the like that has a limited lifetime. Therefore, if the primary power source fails for an extended period of time, the auxiliary power source may also fail causing the latching elements to lose the data stored therein.
Another approach for minimizing the loss of data after a power failure is to maintain an audit trail for each transaction submitted to the system. In such a system, an audit trail is periodically written to a non-volatile storage medium such as a magnetic tape or hard drive. The audit trail typically includes a listing of the status of each transaction that is submitted to the processor. If the power fails, the latching elements within the system lose the data stored therein, as described above. However, after power is restored, the audit trail can be used to reconstruct the status of each transaction. Only those transactions that were not completed and stored must be re-submitted for processing. This can significantly reduce the amount of data re-processing required after a power failure. However, significant time and resources are typically required to read the audit trail data and determine the status of each transaction.
It would be desirable, therefore, to provide a latching element that does not lose data when power is lost or otherwise interrupted. This may reduce the need to provide an auxiliary power source and/or audit trail system or the like.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing a bi-stable latching element that assumes a known initial state. The present invention also provides a latching element that does not lose data when power is lost or otherwise interrupted. This is preferably accomplished by incorporating one or more magnetic elements into the latching element. The magnetic elements have at least two stable magneto-resistive states. By programming the magnetic elements to appropriate resistance values, the latching element may assume a desired or known initial state. By programming the magnetic elements each time the latching element is written during normal functional operation, the data stored therein may not be lost when power is lost or otherwise interrupted.
In one illustrative embodiment of the present invention, a non-volatile latch is provided that has a first supply terminal and a second supply terminal. To store a bit of data, the latch preferably includes a first inverting logic element and a second inverting logic element coupled together in a cross-coupled configuration, wherein each of the first and second inverting logic elements has a power supply terminal and a ground terminal. A first magnetic element is then interposed between the power supply terminal of the first inverting logic element and the first supply terminal of the latch. The first magnetic element provides a first magnetically programmable resistance value. A second magnetic element is interposed between the ground terminal of the first inverting logic element and the second supply terminal of the latch. Likewise, a third magnetic element is interposed between the power supply terminal of the second inverting logic element and the first supply terminal of the latch. Finally, a fourth magnetic element is interposed between the ground terminal of the second inverting logic element and the second supply terminal of the latch.
The magnetically programmable resistance value of the first and fourth magnetic elements is preferably programmed to one of the two stable resistive states, and the magnetically programmable resistance values of the second and third magnetic means is preferably programmed to the other one of the two stable states. This configuration provides a maximum imbalance in the latch, and thus provides the most margin for causing the latch to assume a desired initial state.
The first inverting logic element and the second inverting logic element are preferably conventional inverter circuits, each having a p-channel transistor connected in series with an n-channel transistor. Because the difference in resistance between the two stable resistive states of many magneto-resistive elements is relatively small, the variation in transistor parameters of the n-channel and p-channel transistors can significantly effect the margin of the latch in assuming the desired initial state. To minimize the effect of such transistor parameter variations, magnetic elements are preferably placed in series with both the power supply terminal and the ground terminal of each inverting logic element, as described more fully below.
It is also contemplated that a write circuit may be provided for forcing the latch into an intermediate state, and for releasing the latch so that the latch can assume the state dictated by the magnetic elements. The write circuit may include an n-channel transistor that is coupled between the input of the first inverting logic element (the output of the second inverting logic element) and the input of the second inverting logic element (the output of the first inverting logic element). When the n-channel transistor is turned-on, the voltage of the inputs and outputs of the cross-coupled first and second inverting logic elements is forced to be in an intermediate state. When the n-channel transistor is subsequently turned-off, the latch assumes a desired one of two stable states, depending on the resistive states of the magnetic elements. The n-channel transistor, therefore, allows the latch to be written to the state dictated by the resistive states of the magnetic elements without having
Fulkerson David E.
Gadbois Jason B.
Hurst, Jr. Allen T.
Lu Yong
Sather Jeffrey S.
Auduong Gene N.
Fredrick Kris T.
Honeywell Inc.
Nelms David
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