Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-22
2001-01-30
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S583000, C438S596000
Reexamination Certificate
active
06180474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to an improved method for fabricating a semiconductor device which can facilitate the semiconductor device to be operated at a high speed by reducing a wiring resistance of a gate electrode.
2. Description of the Background Art
In general, in order to operate a semiconductor device at a high speed, there has been known a technique of forming a tungsten suicide layer on a polysilicon layer which is a gate electrode of a peripheral circuit transistor of a semiconductor memory integrated circuit devices. In addition, there has been known a technique of forming a self-aligned silicide, namely a salicide layer on a source/drain of the peripheral circuit unit transistor.
FIG. 1
illustrates a structure of a peripheral circuit unit transistor of a conventional semiconductor device. Referring to
FIG. 1
, a gate insulation film
11
is formed on a semiconductor substrate
10
. A gate electrode
12
is formed on the gate insulation film
11
. The gate electrode
12
includes a polysilicon layer
12
a
and a tungsten silicide
12
b
formed thereon. A sidewall spacer
14
is formed on the semiconductor substrate
10
at the both sides of the gate electrode
12
. An impurity layer
13
having a shallow junction which is called a lightly doped drain LDD is formed in the semiconductor substrate
10
below the sidewall spacer
14
. An impurity layer
15
having a deep junction which is called a source/drain is formed in the semiconductor substrate
10
beside the impurity layer
13
. A self-aligned silicide layer
16
is formed on the gate electrode
12
and the source/drain
15
.
However, in the gate electrode structure of the conventional semiconductor device, the tungsten silicide layer is formed on the polysilicon layer, and thus an integration degree of the semiconductor device is increased. Accordingly, when the gate electrode is reduced in size, the polysilicon layer and the silicide layer are also decreased in size, and thus the wiring resistance of the gate electrode cannot be effectively controlled.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved method for fabricating a semiconductor device which can restrict an increase of a wiring resistance of a gate electrode by raising a ratio of a surface area of a silicide layer to a surface area of a polysilicon layer, even if the gate electrode is reduced in size.
In order to achieve the above-described object of the present invention, there is provided a method for fabricating a semiconductor device which forms a silicide layer at both sidewalls of a gate electrode.
The method for fabricating the semiconductor device includes: a step of forming a gate insulation film on a semiconductor substrate; a step of forming a conductive film on the gate insulation film; a step of forming a conductive film post by patterning the conductive film; a step of forming a first silicide layer at sidewalls of the conductive film post; a step of forming a first impurity layer in the semiconductor substrate at both sides of the conductive film post; a step of forming a sidewall spacer beside the first suicide layer formed at the sidewalls of the conductive film post; and a step of forming a second impurity layer in the semiconductor substrate outside the sidewall spacer.
REFERENCES:
patent: 5227320 (1993-07-01), Johnson et al.
patent: 5256585 (1993-10-01), Bae
patent: 5686329 (1997-11-01), Chang et al.
patent: 6063681 (2000-05-01), Son
Dang Trung
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
LandOfFree
Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2486473