Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1999-01-04

2001-05-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000

Reexamination Certificate

active

06235606

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region.
2. Description of the Related Art
Shallow trench isolation (STI) technique is widely used in a fabrication process for isolating complementary metal oxide semiconductors (CMOSs). A shallow trench isolation is formed by anisotropic etching the substrate to form a trench between a PMOS and an NMOS, followed by filling the trench with silicon oxide.
However, as the number of semiconductor devices increases and the linewidth of fabricating process is reduced, misalignment often occurs during a step of forming a metallic line. Once the misalignment occurs, the conductive line easily makes contact with a source/drain region of the MOS, which decreases the isolation ability of the shallow trench isolation. In addition, if the size of source/drain region is smaller than the size of the metallic line, the metallic line also easily makes contact with the source/drain region. In order to maintain the isolation ability of the shallow trench isolation, it becomes necessary to form a shallow trench isolation which can be utilized for a borderless contact fabrication process in the integrated circuit.
FIGS. 1A through 1H
are schematic, cross-sectional views showing a conventional method of fabricating a shallow trench isolation used in a borderless contact fabrication process.
In
FIG. 1A
, a pad oxide layer
102
and a silicon nitride layer
104
are formed in sequence over a silicon substrate
100
. The pad oxide layer
102
, the silicon nitride layer
104
, and the silicon substrate
100
are patterned. A trench
101
is formed in the silicon substrate
100
. A liner oxide layer
106
is formed on the silicon substrate
100
exposed in the trench
101
.
In
FIG. 1B
, an oxide layer
108
is formed over the silicon nitride layer
104
to fill the trench
101
.
In
FIG. 1C
, chemical-mechanical polishing (CMP) is performed to remove a portion of the oxide layer
108
until the silicon nitride layer
104
is exposed.
In
FIG. 1D
, the silicon nitride layer
104
and the pad oxide layer
102
are removed. A shallow trench isolation
109
is formed. The shallow trench isolation
109
is composed of the liner oxide layer
106
and the oxide layer
108
.
In
FIG. 1E
, a P-well
116
is formed in the substrate
100
and next to the shallow trench isolation
109
. An NMOS is formed on the P-well
116
of the substrate
100
. The NMOS comprises a gate
122
formed on the substrate
100
, and a source/drain region
120
in the silicon substrate
100
beside the gate
122
.
In
FIG. 1F
, a silicon nitride layer
110
is formed over the substrate
100
to cover the shallow trench isolation
109
and the gate
122
. An interlayer dielectric
112
is formed over the silicon nitride layer
110
.
In
FIG. 1G
, a patterned photoresist layer
114
is formed on the interlayer dielectric
112
. The patterned photoresist layer
114
is used as a mask when the interlayer dielectric
112
exposed by the patterned photoresist layer
114
is patterned. The interlayer dielectric
112
is patterned until the silicon nitride layer
110
is exposed. An opening
115
is formed.
In
FIG. 1H
, the silicon nitride layer
110
exposed by the opening
115
is removed. The patterned photoresist layer
114
is removed. A metallic contact opening
117
is formed. However, over-etching often occurs while removing the silicon nitride layer
110
. In this situation, the oxide layer
108
in the shallow trench isolation is easily removed when an opening
115
is misaligned. The thickness of the oxide layer
108
may even lose as much as about 500 Å, which reduces the isolation distance
118
between the contact opening
117
and the PN junction
119
. Once the isolation distance
119
is reduced, junction leakage may occur. Thus, the possibility for device failure increases.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method of fabricating a shallow trench isolation which can be utilized in a borderless contact fabrication process.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a shallow trench isolation fabrication method. The shallow trench isolation of the invention comprises formation of a pad oxide layer and a mask layer over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation. A well of a first conductive type is formed in the substrate of and next to the shallow trench isolation. A metallic oxide semiconductor (MOS) of a second conductive type is formed on the well. The MOS has a conductive region in the substrate. A stop layer is formed over the substrate to cover the MOS and the shallow trench isolation. An interlayer dielectric layer is formed over the substrate to cover the stop layer. The interlayer dielectric is patterned to form an opening until the stop layer is exposed. The opening is above the conductive region. The stop layer exposed by the opening is removed.
In the invention, the etching rate of the isolation layer is lower than the etching rate of silicon oxide or silicon nitride. The material of the isolation layer
208
preferably is silicon-rich oxide or silicon-rich nitride.
is It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5843820 (1998-12-01), Lu
patent: 6008108 (1999-12-01), Huang et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6060357 (2000-05-01), Lee
patent: 6110795 (2000-08-01), Liao

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