Method of passivating a metal line prior to deposition of a...

Details Method of passivating a metal line prior to deposition of a... Method of passivating a metal line prior to deposition of a...

1999-10-22

2001-06-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S688000, C438S637000, C438S658000, C438S654000

Reexamination Certificate

active

06242338

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to protect a metal interconnect structure, from the reactants contained in an overlying, low k dielectric layer.
(2) Background of the Invention
The use of low k dielectric layers, as passivating, or isolating layers, have allowed increases in device performance to be realized, as a result of decreases in the capacitance component of the RC value. Low k dielectric layers, such as hydrogen silsesquioxane, (HSQ), with a dielectric constant between about 2.8 to 3.0, as well as fluorinated silica glass, (FSG), with a dielectric constant between about 3.4 to 4.0, are among a group of materials used for intermetal dielectric, (IMD), layers, resulting in decreased capacitance when compared to dielectric layers comprised with higher dielectric constants. The ability to conformally coat metal interconnect structures, and to easily fill the spaces between these metal interconnect structures, make the use of plasma enhanced chemical vapor deposited, FSG layers, attractive as a IMD layer. However the high mobility of fluorine ions, present in the FSG layer, and the affinity of the fluorine ion to moisture, can result in the formation of hydrofluoric, (HF), acid, at the FSG-metal interconnect interface. The presence of HF can in turn result in corrosion of, or damage to, the exposed, underlying metal interconnect structure, which can be comprised of aluminum —copper, tungsten, titanium, or titanium nitride. In addition to the corrosion, or damage phenomena, bubbling at the FSG-metal interconnect interface, can also occur, resulting in peeling, or delamination of the an insulator layer, such as FSG, from an underlying metal interconnect structure.
This invention will teach a process in which the surface of the metal interconnect structure is passivated, prior to deposition of the FSG layer. At the conclusion of the metal etch, post clean cycle, a plasma treatment, using N
2
O, N
2
/H
2
, NH
3
, or H
2
O, is performed resulting in the formation of a thin metal oxide, or metal nitride layer, protecting the underlying metal interconnect structure from the HF effects, caused by the halogens contained in a subsequent, overlying low k dielectric layer, such as FSG. Prior art, such as Guo et al, in U.S. Pat. No. 5,763,010, describe a degassing step, performed after deposition of the FSG layer, however that prior art does not teach the plasma treatment, of a metal surface, prior to FSG deposition.
SUMMARY OF THE INVENTION
It is an object of this invention to use a low k dielectric layer, as a interlevel dielectric layer, overlyig metal interconnect structures.
It is another object of this invention to perform a plasma treatment, in a nitrogen containing, or in a moisture, or water containing, ambient, to the exposed surfaces of the metal interconnect structure, prior to deposition, or application, of a low k dielectric layer.
It is still another object of this invention to perform a plasma treatment, in a nitrogen containing, or water containing, ambient, in situ, at the conclusion of the post metal clean procedure, to form a protective layer, on the exposed surfaces of the metal interconnect structures, prior to the deposition of, or the application of, a low k dielectric layer.
In accordance with the present invention a method of protecting metal interconnect structures, from halogen build-up, at the interface of a halogen containing, low k dielectric layer metal interconnect structure, is described. After patterning of a metal, or composite metal layer, the defining photoresist layer is removed via plasma oxygen ashing procedures. This is followed by an in situ, plasma treatment, performed in a nitrogen containing, or a water containing ambient, resulting in the formation of a thin metal nitride, or metal oxide layer, on the exposed surfaces of the metal interconnect structures. The plasma treatment can also be performed in a separate tool. A low k dielectric layer, such as a halogen containing, FSG layer, is then deposited, or applied, with the thin metal nitride, or metal oxide layer, protecting the underlying metal interconnect structures, from halogen ions, located in the low k dielectric layer.


REFERENCES:
patent: 5656543 (1997-08-01), Chung
patent: 5877557 (1999-03-01), Zawaideh

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