Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-16
2001-01-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S581000, C438S585000
Reexamination Certificate
active
06180477
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103136, filed Mar. 2, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a field effect transistor (FET).
2. Description of the Related Art
A field effect transistor (FET) is an important device in Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) fabrication process. The FET comprises a gate oxide layer formed on a substrate, a gate formed on the gate oxide layer, a spacer beside the gate on the gate oxide layer, and a source/drain region beside the gate in the substrate. When the FET is operated, an electrical field is generated by applying a voltage to the gate. The electrical field is used to control a channel, which is between the source region and the drain region. For example, if channel is turned on, the electrons flow from the source region to the drain region. In contrast, if the channel is turned off, the electrons cannot flow between the source region and the drain region. Therefore, the on or off state of the channel controls the connection or disconnection of the electrical circuit.
Because the integration of semiconductor devices increases, there is a corresponding size reduction in the FET. However, size reduction causes problems, arising from a gate fringing electric field, to occur. When the FET is operated, the voltage is applied to the gate. A potential difference between the gate and fringing devices occurs. Thus, an electrical field, which is specifically called a fringing electrical field, is generated. Typically, the spacer provides isolation to reduce the fringing electrical field effect on the fringing devices near the FET. However, as the size of device decreases, the gate fringing electrical field effect becomes especially obvious. Even when the gate is operated with a low voltage, the gate fringing electrical field still greatly affects the FET.
The gate fringing electrical field effect enhances the FET to attract a portion of the electrons, which portion is supposed to flow from the source region to the drain region, into the gate. This phenomenon of electrons move from drain side to gate is called a hot electron effect. The hot electron effect leads to threshold voltage drift and results in a device performance degradation. The lifetime of device and circuit is therefore decreased.
FIG. 1
is a schematic, cross-sectional view showing a conventional FET and the fringing electric field.
In
FIG. 1
, a patterned gate oxide layer
110
is formed on a substrate
100
. A gate
106
is formed on a portion of the gate oxide layer
110
. A spacer
108
is formed beside the gate
106
on the gate oxide layer
110
. A source region
102
and a drain region
104
are formed beside the gate
106
in the substrate
100
. A silicide layer
112
is formed on the source region
102
and the drain region
104
, so as to connect other circuits (not shown).
While the FET is operated, a voltage is applied to the gate
106
. The electrical potential of the gate
106
is higher than that of the silicide layer
112
on the source region
102
and the drain region
104
. This, in turn, causes a gate fringing electric field
114
to occur. Once the spacer
108
cannot effectively isolate the gate fringing electric field
114
, a portion of the electrons is attracted to the gate
106
and leads to a hot electron effect.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a field effect transistor. A gate oxide layer is formed on a substrate. A gate is formed on the gate oxide layer. A first spacer is formed beside a sidewall of the gate. A source region and a drain region are formed beside the first spacer in the substrate. A preserve layer is formed over the substrate. A polysilicon layer is formed to cover the preserve layer. A portion of the polysilicon layer is removed to form a polysilicon spacer. A portion of the preserve layer exposed by the polysilicon spacer is removed. A metallic layer is formed on the source region, the drain region, the gate, the first spacer, the preserve layer, and the polysilicon spacer. A thermal step is performed. The metallic layer reacts with the polysilicon spacer to form a second spacer. A self-aligned silicide layer is formed on the source region, the drain region, and the gate. The remaining metallic layer is removed.
In the invention, the material of the second spacer is silicide. Since the second spacer and the gate are both conductive materials, the gate fringing electric field is preserved between the gate and the second spacer. Thus, the gate fringing electric field does not interfere with the source region and the gate region. The hot electron effect and the breakdown effect of FET do not occur.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5102815 (1992-04-01), Sanchez
patent: 5256585 (1993-10-01), Bae
patent: 5424572 (1995-06-01), Solheim
patent: 5451532 (1995-09-01), Bashir et al.
patent: 5581114 (1996-12-01), Bashir et al.
patent: 5679589 (1997-10-01), Lee et al.
patent: 5972763 (1999-10-01), Chou et al.
Huang Jiawei
J.C. Patents
Lindsay Jr. Walter L.
Niebling John F.
United Silicon Incorporated
LandOfFree
Method of fabricating field effect transistor with silicide... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating field effect transistor with silicide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating field effect transistor with silicide... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2482382