Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-24
2001-05-15
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S231000, C438S291000, C438S305000
Reexamination Certificate
active
06232164
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a MOS semiconductor devices and more particularly to a method of forming a MOS device having a localized anti-Short Channel Effect (SCE) block region (e.g., anti-punchthrough region) which is not in contact with the source/drain regions to reduce parasitic Junction capacitance.
2) Description of the Prior Art
Metal-Oxide-Silicon (MOS) transistors such as Field Effect Transistors, MOSFETs, are well known in the art. Such devices are typically formed having a source region and a drain region, of similar conductivity type, separated by a channel region, of a differing conductivity type, capped with a conductive gate. The gate to source voltage controls the passage of current through the channel between the source and the drain regions. In typical n-channel operation, a positive voltage is applied between the drain and the source with the source grounded to a reference potential. Due to the differing conductivity type of the channel separating the source and the drain, usually no current flows between the source and drain. However, if a sufficiently large voltage is applied between the gate and source, the conductivity in the channel region will increase, thereby allowing current to flow between the source and the drain. The gate voltage required to induce the flow of current between the drain and the source is referred to as the threshold voltage.
Under certain circumstances, however, unwanted current flow may occur between the source and the drain even when no voltage is applied to the gate. Such a condition may be due to avalanche breakdown or punchthrough. Punchthrough occurs when the MOS transistor is biased in an off state with the gate and the source both at approximately zero volts with respect to ground, but with the drain at a voltage as high as 5 volts. Even though no flow of current is desired, drain current may still occur regardless of the zero gate voltage. This is due to the fact that under such conditions, the normal doping concentration of the channel region is not sufficient to prevent current flow between the source and drain regions.
In order to eliminate punchthrough currents, the doping concentration in the substrate of the MOS device is raised. A high energy or so-called “punchthrough” implant is used to locally raise the doping concentration of the MOS device substrate. Typically, the “punchthrough” implant is made as a blanket implant over the active region of the MOS device. Unfortunately, the punchthrough implant also raises the doping concentration of the substrate in the source and drain region. As a consequence of the increased doping concentration, the source-drain junction capacitance is also increased.
Furthermore, MOS semiconductor transistors, such as MOSFETs, often experience current leakage and other problems due to short channel lengths. The short channel, which occurs as a consequence of difficult to control manufacturing processes, results in closely spaced source and drain regions. Due to the close proximity of the source to the drain, current leakage or other “short channel” effects may hamper the performance of the semiconductor device.
Consequently, a need exists to prevent punchthrough effects in semiconductor devices such as MOSFETs using a high energy or punchthrough implant without substantially increasing source-drain junction capacitance, and which minimizes short channels effects.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,399,508 (Nowak) Method for self-aligned punchthrough implant using an etch-back gate—shows a anti-punchthru process. See Nowak,
FIGS. 1D-1F
and Col. 4.
U.S. Pat. No. 5,489,543 (Hong) shows a method of forming an anti-punchthru region by implanting through a polysilicon layer
24
.
U.S. Pat. No. 5,270,234 (Huang) Deep submicron transistor fabrication method—shows a method of forming an anti-punchthru region
220
by forming spacers
65
55
on the sidewalls of a masking layer
40
.
U.S. Pat. No. 5,434,093 (Chau) Inverted spacer transistor—teaches a method for forming narrow length transistors by an inverse spacer process.
U.S. Pat. No. 4,011,105 (Paivinen): Field inversion control for N-channel device integrated circuits—discloses another method of forming a P region under the gate of a NMOS TX. U.S. Pat. No. 5,550,074 (Lin) shows a method of forming an anti-punchthru region by a separate masking process.
However, there is still a need for further reduction of the SCE.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a MOS transistor having an Anti-SCE block region that reduces the Short Channel Effect (SCE).
It is an object of the present invention to provide a method for fabricating a MOS transistor having an Anti-SCE block that reduces the Short Channel Effect (SCE) and a method for forming a metal gate.
It is another object of the invention to form a high dose Anti-SEC that does not directly contact (or overlap) S/D regions thereby the parasitic junction capacitance can be reduced and the device speed can be reduced.
It is another object of the invention to form an Anti-SCE region under a metal gate.
To accomplish the above objectives, the present invention provides a method of manufacturing a MOS transistor having an anti-punchthru region (or Anti-SCE block) formed by a self-aligned ion implant (I/I) that reduces the SCE. The method begins by forming isolation regions in the substrate defining active regions. Next, we form a sacrificial oxide layer over the active areas. A masking layer is then formed over the substrate. The masking layer is formed having a first opening defining a channel region in the substrate. Following this we perform Anti-SCE block implant through the first opening to create an anti-SCE region doped with a first conductivity type impurity. The sacrificial oxide in first opening is removed. The, we form a gate dielectric layer on the substrate in the first opening. A gate is formed over the gate dielectric layer. The gate is planarized stopping on the masking layer. The masking layer is dielectric layer. The gate is planarized stopping on the masking layer. The masking layer is removed. A LDD Implant is performed by implanting ions into the substrate in the active areas adjacent to the metal gate stack to form LDD regions doped with ions having a second conductivity type doping. A spacer is formed on the sidewall of the gate. We next perform a S/D implant to form Source/Drain regions adjacent to the metal gate stack. The source/drain regions have a second conductivity type doping.
The invention provides the following benefits:
lowers the gate resistance by forming a metal gate
the anti-SCE block region lowers the junction capacitance
the anti-SCE block region reduces the Short channel effect (SCE)
the anti-SCE block region reduces the hot carrier effect.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 4011105 (1977-03-01), Paivinen et al.
patent: 5270234 (1993-12-01), Huang et al.
patent: 5399508 (1995-03-01), Nowak
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5489543 (1996-02-01), Hong
Tsai Chaochieh
Wang Kuan-Yao
Ackerman Stephen B.
Fourson George
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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