Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-10
2001-05-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S264000
Reexamination Certificate
active
06232184
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing the floating gate of a stacked-gate nonvolatile memory unit such that the floating gate has a better external profile and the memory unit has a higher performance.
2. Description of the Related Art
Stacked-gate nonvolatile memory can be classified roughly into erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory. All these memories use an isolated or floating gate as the place for storing electric charges. When the floating gate contains electric charges, a logic state of ‘1’ is assumed. On the other hand, if no electric charges are present, the memory is assumed to be in a logic state of ‘0’ by default. To tore electrons inside the floating gate, the electrons have to pass through a tunneling oxide layer. Therefore, the thickness of the tunneling oxide layer is one of the critical factors in determining how many electrons can pass through. If the tunneling oxide layer is too thick, very few electrons are able to pass through and there will not be enough electrons inside to indicate a logic state of ‘1’.
FIG. 1
is a schematic cross-sectional view showing the floating gate of a conventional stacked-gate type nonvolatile memory unit. A gate oxide layer
110
and a polysilicon floating gate
120
are formed over a substrate
100
. After the floating gate
120
is patterned, a silicon oxide layer
130
is formed over the floating gate
120
by performing a thermal oxidation. An oxide
itride/oxide (ONO) composite layer (not shown in the figure) is next formed over the silicon oxide layer
130
serving as interpolysilicon dielectrics (IPD).
However, during thermal oxidation, the lower edge portion
140
of the floating gate
120
is likely to be over-oxidized due to oxygen diffusion. Consequently, a thicker layer of oxide is formed having a shape very similar to a bird's beak formation when a field oxide layer is formed on a substrate by oxidation. In addition, the portion of the oxide layer
110
below the floating gate
120
is actually a channel (i.e. the tunneling oxide layer
115
) through which hot electrons move in and out of the floating gate
120
. As miniaturization of devices continues, the tunneling oxide layer
115
will contain a proportionally greater amount of thick oxide layer
140
so that hot electrons enter and leave the floating gate
120
with greater difficulty. Consequently, writing data into or erasing data from a nonvolatile memory unit becomes more unreliable.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of manufacturing the floating gate of a stacked-gate nonvolatile memory unit such that the floating gate has a better external profile and the memory unit has a higher performance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. The floating gate is chemical dry etched to form a floating gate whose bottom section is slightly wider than the top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.
According to the method of this invention, the polymer deposited during the first etching operation is able to protect the bottom portion of the floating gate. Therefore, when an isotropic chemical dry etching operation is subsequently carried out, the bottom portion of the floating gate will be wider. Because oxygen atoms can only penetrate up to a certain depth, there is no thickening of oxide near the edge of the gate oxide layer (or the tunneling oxide layer) at the bottom of the floating gate after thermal oxidation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4397077 (1983-08-01), Derbenwick et al.
patent: 4945068 (1990-07-01), Sugaya
patent: 6057197 (2000-05-01), Sung
Lin Chingfu
Wang Ling-Sung
Bowers Charles
Huang Jiawei
J. C. Patents
Pert Evan
Taiwan Semiconductor Manufacturing Co. Ltd.
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