Multi-step plasma process for forming TiSiN barrier

Details Multi-step plasma process for forming TiSiN barrier Multi-step plasma process for forming TiSiN barrier

2000-04-04

2001-08-07

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S685000, C438S686000

Reexamination Certificate

active

06271136

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a robust method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of an improved copper metal diffusion barrier layer, TiSiN, by a combination of metal-organic chemical vapor deposition (MOCVD) and multi-step plasma treatment that improves the diffusion resistant properties of the barrier layer (at both interfaces or surfaces) for both copper and silicon diffusion, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias.
2. Description of Related Art
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 5,770,520 (Zhao et al.) describes a TiSiN barrier layer comprising: N source, Si source and Ti source TiSiN barrier layer and form a Cu plug over TiSiN barrier layer. Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistively of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of gram boundaries which are believed to provide the diffusion paths through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti—Si—N material formed using a source of titanium, a source of silicon, and a source of nitrogen, all in a chemical vapor deposition (CVD) system and by CVD techniques. Optional TiSiN deposition is outlined using plasma enhanced chemical vapor deposition (PECVD) using titanium organic precursors.
U.S. Pat. No. 5,851,367 (Nguyen et al.) describes a process to deposit TiSiN and then Cu over surfaces in a dual damascene structures. A method for selectively applying CVD copper to metallic surfaces, that are co-located with non-metallic surfaces, is described. After CVD deposition of copper and through a number of repeated cycles of etching and copper deposition, the copper overlying the metallic surface is accumulated to achieve the desired thickness; while the non-metallic surface remains free of copper. A method is also provided for the selective deposition of copper on metallic surfaces to fill interconnects in damascene IC structures. An IC with a copper layer overlying a metallic surface, co-located with a non-metallic surface, where the copper layer is grown through repeated cycles of ion etching and copper deposition, is also described.
U.S. Pat. No. 5,918,150 (Nguyen et al.) describes a process to deposit TiSiN and then Cu over surfaces. A method for etching metallic surface on an integrated circuit (IC) is described to minimize electrical resistance between the metallic surface and subsequently applied chemical vapor deposition (CVD)) copper. The metallic surface is etched with the ions of an inert gas, such as Ar, at low energy levels. An IC comprising a copper stud to interconnect dielectric interlevels with improved electrical conductivity is also described. In one embodiment, the copper stud is interfaced to diffusion barrier material and in another embodiment the copper stud is interfaced to a metallic surface.
U.S. Pat. No. 5,976,928 (Kirlin et al.) describes a “barrier saver” in a method of fabricating a ferroelectric capacitor structure by sequentially depositing a bottom electrode layer, a ferro-electric layer and a top electrode layer on a be structure. Optionally, with deposition of a layer of a conductive barrier material beneath the bottom electrode layer, to form a capacitor precursor structure, and planarizing the capacitor precursor structure by chemical mechanical polishing to yield the ferro-electric capacitor structure.
U.S. Pat. No. 5,913,144 (Nguyen et al.) teaches an oxygen containing plasma treatment of a TiN, TiON, TiSiN, TaSiN, TaN, TiW, TiWN, Mo, and WN and other barrier layers. The method claims improvement of adhesion of copper to the diffusion barrier material, such as TiN, in an integrated circuit substrate. The diffusion barrier is exposed to either a reactive oxygen species, or a plasma containing oxygen. A thin layer of the diffusion barrier is oxidized, typically less than 50 A, in response to exposure to the oxygen environment. CVD copper is then deposited over the oxidized diffusion barrier surface. The oxide layer improves bonding between the copper and diffusion barrier surfaces. The oxide layer permits the control of tolerances in the diffusion barrier preparation processes, and copper precursor, to be relaxed. An integrated circuit comprising an oxide layer between the diffusion barrier and the copper layer is also provided.
U.S. Pat. No. 5,824,599 (Schacham-Diamand et al.) describes a TiN barrier layer for a Cu interconnect. A method for utilizing electroless copper deposition is described to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper need layer is conformally blanket deposited in vacuum over the barrier layer. After a dual damascene process with chemical mechanical polish (CMP) back of the excess conducting material and barrier material, the only remaining material are copper and barrier material inlaid in the via/trench openings. Then, an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved robust method of forming a copper metal diffusion barrier layer, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias. The formation of an improved copper metal diffusion barrier layer, TiSiN, is fabricated by using a combination of metal-organic chemical vapor deposition (MOCVD) and multi-step plasma treatment that improves the diffusion resistant properties of the barrier layer at both interfaces (for both copper and silicon) and improves adhesion properties in both single and dual damascene processes. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications. This invention makes good use of metal-organic chemical vapor deposition (MOCVD) combined with multi-step plasma treatment and a plasma-enhanced deposition.
For completeness provided by the present invention, is a semiconductor substrate with an insulating layer thereon. A copper metal interconnect typically is patterned within an insulating layer. In addition, a layer of interlevel dielectric (ILD) is deposited and patterned into a trench structure or “gap” opening. Provided can be both a single and dual damascene structure. The insulating material is typically silicon oxide compounds. Polysilicon gate structures (with silicides) and source/drain diffusions are typically upon or in a single crystal silicon substrate or IC module.
The first embodiment of the present invention is the deposition by metal-organic chemical vapor deposition (MOCVD) of the initial copper metal diffusion barrier layer, which consists of the following titanium precursor materials: TDMAT (tetrakis (dimethylamido) titanium), having the formula Ti[N(CH
3
)
2
]
4
, TDEAT (tetrakis (diethylamido) titanium) having the formula Ti[N(CH
3
CH
2
)
2
]
4
, Ti[NR]
4
type compounds, and titanium tetrachloride, formula TiCl
4
. Prior to the reduction of these precursor materials, the substrates undergo a thermal heating step in which the substrates are heated up to from approximately 200 to 450° C. Next, the substrates undergo a metal-organic chemical vapor deposition (MOCVD), whi

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