Method of forming a flash memory

Details Method of forming a flash memory Method of forming a flash memory

1999-10-21

2001-05-15

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000, C438S266000, C438S424000, C438S427000

Reexamination Certificate

active

06232181

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a flash memory. More particularly, the present invention relates to a method of forming the shallow trench isolation (STI) structures and buried bit lines of flash memory.
2. Description of Related Art
Shallow trench isolation (STI) is an important technique for isolating small dimensional devices on a silicon chip. However, forming STI structures on a substrate with buried N+ bit lines is no easy operation. There are two main reasons:
1. The buried bit lines and the active regions are perpendicular to each other; and,
2. If the buried bit lines are formed before etching out the trenches of STI structures, each continuous buried bit line will be cut into multiple segments.
Since the active regions and the buried bit lines are mutually perpendicular, the silicon nitride hard mask layer for patterning the active region and etching out trenches generally consists of a plurality of silicon nitride lines with portions of each buried bit line exposed. If the silicon nitride hard mask is used as an etching mask for producing the trenches, the buried bit lines will be cut into several discontinuous segments so that the original function of conducting an electric current is lost.
SUMMARY OF THE INVENTION
The present invention provides a method capable of producing the plurality of bit lines, the gate oxide layer and the gate structures of a flash memory.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming flash memory. A silicon substrate is first provided. A pad oxide layer is formed over the substrate. A plurality of silicon nitride lines parallel to each other is formed over the pad oxide layer. The silicon nitride lines have a plurality of openings that expose the pad oxide layer. Using the silicon nitride lines as a mask, ions are implanted into the substrate via the openings to form a plurality of bit lines. Silicon dioxide is next deposited into the openings to form a silicon dioxide layer that fills the openings and covers the plurality of bit lines. A photoresist layer is formed over the silicon nitride lines and the silicon dioxide layer. The photoresist layer is patterned to form a plurality of mutually parallel lines in a direction perpendicular to the silicon nitride lines. Using the photoresist lines as a mask, the silicon nitride lines, the pad oxide layer and the substrate are etched to form a plurality of trenches between the bit lines. Oxide plugs are next formed in the trenches, and then the silicon nitride lines and the pad oxide layer are removed sequentially. Finally, a gate oxide layer is formed over the aforementioned gate structures.
In this invention, lines of protective silicon dioxide are formed over the buried bit lines before the trench-forming step is carried out. Hence, the buried bit lines are still capable of conducting a current after STI structures are formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6048788 (2000-04-01), Ding et al.
patent: 6100161 (2000-08-01), Yu et al.
patent: 6150234 (2000-11-01), Olsen
patent: 6171909 (2000-08-01), Ding et al.

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