Method of making an IGFET with elevated source/drain regions...

Details Method of making an IGFET with elevated source/drain regions... Method of making an IGFET with elevated source/drain regions...

1997-04-21

2001-03-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S307000, C438S592000

Reexamination Certificate

active

06197645

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to forming insulated-gate field-effect transistors with elevated source/drain regions.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation, and then the implanted dopant is activated using a high-temperature anneal that would otherwise melt the aluminum.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the sidewalls of the gate, and a heavy implant is self-aligned to spacers adjacent to the sidewalls of the gate. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
There are, however, several drawbacks to using ion implantation. A phenomena called “channeling” may occur when the ion beam which implants the dopants is closely aligned with the crystal lattice of the silicon. When channeling occurs, the dopants are initially implanted deeper beneath the top surface of the substrate, but then as implantation continues the substrate surface becomes amorphous and less channeling occurs. Unfortunately, the depth of the channeled dopants is difficult to control. Channeling can be avoided by tilting the substrate (typically, at an angle of 7°) with respect to the ion beam. However, implanting off-axis can cause asymmetric doping of the source and drain regions.
Another drawback of ion implantation is random scattering of the implanted dopants. The random scattering results in a small portion of implanted regions, measured as the “lateral straggle,” being disposed beneath the mask.
A further drawback of ion implantation is that the concentration (or doping profile) of the implanted dopants typically forms a gaussian distribution along the vertical axis in which the peak concentration is substantially below the top surface of the substrate. Furthermore, driving-in the dopants by high-temperature processing causes the implanted dopants to diffuse farther into the substrate.
A strategy for enhancing IGFET performance is to have the dopant atoms as close to the surface of the substrate as possible. Restricting current flow to a very narrow layer between the source and drain tends to improve current drive properties, and also reduce off-state leakage current. Accordingly, as IGFET dimensions are reduced, it is highly desirable to form shallow channel junctions on the order of 0.01 to 0.10 microns deep in order to improve transistor performance.
Introducing source/drain doping into the substrate by solid phase diffusion from elevated source and drain regions is known in the art. With this approach, after the gate and sidewall spacers are formed, epitaxial silicon is selectively deposited (also referred to as “grown”) on regions of the substrate adjacent to the spacers to form the elevated source and drain regions on the substrate. Thereafter, a dopant is implanted into the elevated source and drain regions, and a thermal cycle is applied to diffuse the dopant from the elevated source and drain regions into underlying source and drain regions in the substrate. As a result, shallow channel junctions can be formed in the substrate without ion implantation. If desired, doped glass spacers can also be utilized to diffuse a dopant into the underlying source and drain regions to assure that the channel junctions are substantially aligned with the sidewalls of the gate. See, for instance, U.S. Pat. No. 5,504,031 to Hsu et al.
A drawback to conventional elevated source and drain structures is that typically the spacers are essential to prevent shorting the elevated source and drain regions to the gate, and the spacers occupy valuable chip area. Although disposable spacers can be employed and subsequently removed, the additional chip area is still required. Another drawback is that the channel length is often limited by the minimum resolution of the photolithographic system, since a substantial overlap between the gate and the source/drain may create unwanted capacitive effects. These drawbacks tend to constrain efforts towards further miniaturizing the device.
Accordingly, a need exists for a method of fabricating an IGFET with shallow source and drain junctions in a manner that provides for further reductions in device size.
SUMMARY OF THE INVENTION
A primary object of the invention is to provide a highly miniaturized IGFET with elevated source and drain regions without the need for sidewall spacers. This is accomplished by disposing the elevated source and drain regions in close proximity to a gate with sloped sidewalls.
In accordance with one aspect of the invention, a method of forming an IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the l

Affiliated with

Also associated with

Rating

Method of making an IGFET with elevated source/drain regions... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making an IGFET with elevated source/drain regions..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making an IGFET with elevated source/drain regions... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2479902