Fabrication of buried channel devices with shallow junction...

Details Fabrication of buried channel devices with shallow junction... Fabrication of buried channel devices with shallow junction...

1998-10-16

2001-01-09

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S289000, C438S290000, C438S291000

Reexamination Certificate

active

06171895

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to devices formed on semiconductor regions having doping profiles designed to adjust the operating characteristics of the device, and to the methods of making such devices.
2. Description of the Related Art
When forming MOS devices, it is conventional to form a buried channel by doping the channel region of the MOS device to adjust the threshold of the MOS device. One type of buried channel used in PMOS devices is formed as illustrated in FIGS.
1
-
3
. In
FIG. 1
, an N-type substrate
10
has a 100-500 Å thick sacrificial oxide layer
12
formed on its surface. The threshold adjust implant is made through the sacrificial oxide into the substrate
10
. The threshold adjust implant may, for example, consist of a boron fluoride (BF
2
) implant at a dosage of 5×10
11
to 1×10
13
per cm
2
with an energy of 30-70 KeV. For those device configurations which require an implantation to prevent punchthrough, an antipunchthrough implant is performed next. First, photoresist is deposited and patterned to define the region for the antipunchthrough implant. Then, phosphorus ions are implanted into the substrate at a dosage of 5×10
11
to 1×10
13
per cm
2
with an energy of 50-250 KeV. The antipunchthrough implant mask is then removed. Regardless of whether an antipunchthrough implant is made or not, the sacrificial oxide
12
is then removed.
Referring to
FIG. 2
, a layer of thermal oxide
14
is grown to a thickness of 50-150 Å on the substrate
10
to serve as a gate oxide layer. A layer of polysilicon
16
is deposited to a thickness of 2000-4000 Å, for use in forming the gate of the PMOS device. Phosphorus ions are implanted into the polysilicon layer
16
and then annealed to thermally activate the implanted dopants. If it is desired, a refractory metal or silicide layer such as WSi
x
or TiSi
x
is then formed on top of the polysilicon to reduce the resistance of the gate electrode material. As shown in
FIG. 3
, a photoresist layer is deposited on the polysilicon, and other layers if present, and the photoresist is patterned to form a gate mask
18
. The polysilicon layer
16
is then etched and processing continues to complete the PMOS device.
CMOS devices consist of a PMOS device and an NMOS device. Performance of both PMOS and NMOS devices typically must be improved to achieve improved CMOS performance. Two problems are of particular concern for improving the performance and reducing the size of MOS devices: the short-channel effect and the segregation of dopants into the gate oxide. It is generally desirable to use a shallow buried channel doping region to avoid the short channel effect, but conventional implantation techniques often have difficulty in reliably producing a suitable channel doping profile. Typically, low energy implantations are used to define a shallow threshold adjust doping profile but such implantations are difficult to control and so are not well suited to mass production. Accordingly, a more readily controlled shallow doping process is desirable.
Conventional attempts to address the segregation of channel dopants into the gate oxide have significant drawbacks. Segregation of dopants from the channel region of the MOS device into the gate oxide may occur during growth of the gate oxide or during other high temperature processes like anneals. To avoid this, low temperature gate oxides are often used in making MOS devices. Such low temperature gate oxides are undesirable because those oxides are of poorer quality and are more prone to pinholes than are oxides grown at higher temperatures. Accordingly, it would be desirable to manufacture MOS devices in a manner compatible with the use of higher temperature gate oxides.
SUMMARY OF THE PREFERRED EMBODIMENTS
In accordance with an aspect of the present invention, a MOS device includes a source, a drain, a gate, a channel region and a gate insulator formed between the channel region and the gate, with the channel region comprising the following regions as a function of depth away from the gate insulator: A first region adjacent the gate insulator is doped with a first dopant of a first conductivity type distributed over a region extending away from the gate insulator, the first dopant having a peak concentration at a depth of less than 0.15 &mgr;m. A second region is formed adjacent the first region. The second region is doped with a second dopant of a second conductivity type having a distribution such that a free carrier concentration of the channel region falls from a peak value adjacent the gate insulator to a value at least ten times smaller than the peak value at a distance within 0.15 &mgr;m from the gate insulator.
A different aspect of the present invention provides a MOS device having a source, a drain, a gate, a channel and a gate insulator formed between the channel and the gate, with the channel comprising a buried channel region adjacent the gate insulator. The buried channel region is doped with a first dopant of a first conductivity type which acts as a threshold adjust implant for the MOS device, the first dopant having a peak concentration at a depth of less than 0.15 &mgr;m. A second region doped with a second dopant of a second conductivity type is formed adjacent the buried channel region. The second dopant has a distribution such that a concentration of dopants of the second conductivity type is equal to a concentration of the first dopant at a distance within 0.15 &mgr;m from the gate insulator.
A different aspect of the present invention provides a PMOS device having a gate, a channel region and a gate insulator formed between the channel region and the gate, the channel region comprising a threshold adjust implant distributed over a first region extending away from a surface of the channel region, the threshold adjust implant comprising a first, P-type dopant having a concentration in excess of any other dopant in the first region. A second region doped with a second, N-type dopant is formed adjacent the first region. The second dopant has a distribution such that a concentration of N-type dopants is equal to a concentration of the first, P-type dopant at a depth of 0.03-0.07 &mgr;m.
A different aspect of the present invention provides a method of making a MOS device comprising the steps of forming a gate oxide over a substrate, depositing a first polysilicon layer over the gate oxide, implanting a threshold adjust dopant of a first conductivity type through the polysilicon layer, through the gate oxide and into the substrate, depositing a second layer of gate material over the first polysilicon layer, and forming a gate electrode mask and etching the second layer of gate material to form a gate electrode. In accordance with a further aspect of the present invention, this method also includes the following steps performed before the formation of the gate oxide: forming a sacrificial oxide layer on a surface of the substrate; implanting into the substrate a dopant of a second conductivity type; and etching the sacrificial oxide to expose the surface of the substrate.
In accordance with another aspect of the present invention, a method of making a PMOS device comprises the steps of forming a gate oxide over a substrate, depositing a first polysilicon layer over the gate oxide, implanting a P-type threshold adjust dopant through the polysilicon layer, through the gate oxide and into the substrate, depositing a second layer of gate material over the first polysilicon layer, and forming a gate electrode mask and etching the second layer of gate material and the first polysilicon layer to form a gate electrode.
According to the present invention, a PMOS device can be made by forming a gate oxide over a substrate, depositing a first polysilicon layer to a thickness of 300-2500 Å over the gate oxide, implanting boron at a density of 3×10
12
to 3×10
13
per cm
2
with an energy of 20-200 KeV through the polysilicon layer, through the gate oxide and int

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