Etch stop layer for dual damascene process

Details Etch stop layer for dual damascene process Etch stop layer for dual damascene process

1997-12-19

2001-09-18

Turner, Archene (Department: 1775)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S597000, C438S598000, C438S618000, C438S689000, C438S735000, C438S736000, C438S763000, C438S778000

Reexamination Certificate

active

06291334

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the fabrication of integrated circuits on substrates. More particularly, the invention relates to a new etch stop layer and a process for forming a dual damascene structure characterized by a low capacitance between interconnect lines.
2. Background of the Invention
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of horizontal interconnects (typically referred to as lines) and vertical interconnects (typically referred to as contacts or vias: contacts extend to a device on the underlying substrate while vias extend to an underlying metal layer such as M
1
, M
2
, etc.) in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology has increased the importance of reducing capacitive coupling between interconnect lines in particular. In order to further improve the speed of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and low k (dielectric constant <4.0) insulators to reduce the capacitive coupling between adjacent metal lines. For example, copper is now being considered as an interconnect material in place of aluminum because copper has a lower resistivity and higher current carrying capacity. Also, dielectric materials having a lower dielectric constant than that of silicon dioxide (dielectric constant ~4.0) are being seriously considered for use in production devices. One example of these dielectric materials is fluorine-doped silicon dioxide also known as fluorine-doped silicon glass (FSG) (dielectric constant ~3.5-3.7).
However, these materials present new problems for IC manufacturing processes. For example, because copper is difficult to etch in a precise pattern, traditional deposition/etch processes for forming interconnects has become unworkable, and accordingly, a process referred to as a dual damascene is being used to form copper interconnects. In a dual damascene process, the dielectric layer is etched to define both the contacts/vias and the interconnect lines. Metal is then inlaid into the defined pattern and any excess metal is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP).
FIGS. 1
a
through
1
c
illustrate one method used in the fabrication of a dual damascene structure using a single (thick) dielectric layer
10
formed on a substrate
12
. The dielectric layer
10
is patterned and etched using a timed etch process to define an interconnect line
20
as shown in
FIG. 1
a
. The vertical interconnects
16
(i.e., contacts/vias), are then patterned in the bottom of the lines (
FIG. 1
b
) and etched to expose an underlying conductive or semiconductive layer such as a substrate
12
(
FIG. 1
c
). The etched structure having contacts/vias
16
and interconnects
20
is filled with a conductive material and the upper surface is planarized. However, the depth of the timed etch step is difficult to control and the patterning of the contacts/vias in the interconnect trenches is also a difficult process to perform.
FIGS. 2
a
and
2
b
illustrate another method used to fabricate a dual damascene structure. As shown in
FIG. 2
a
, a single (thick) dielectric layer
10
is formed on a substrate
12
and the contacts/vias
16
are patterned and partially etched through the dielectric layer
10
using a timed etch process. The interconnect lines
20
are then patterned and a second timed etch is conducted to form the trenches for the interconnects as shown in
FIG. 2
b
. During this second timed etch, the contacts/vias
16
are also etched to an additional depth sufficient for the contacts/vias to extend vertically to their intended depth as shown by the dashed lines. However, the timed etch steps again are difficult to control making this process less attractive for commercial production.
A third and more preferable method for fabricating a dual damascene structure uses a two-step dielectric deposition with an etch stop deposited therebetween as shown in
FIG. 3. A
first dielectric layer
10
is deposited on a substrate and then an etch stop
14
is deposited on the first dielectric layer. The etch stop is then patterned to define the openings of the contacts/vias
16
. A second dielectric layer
18
is then deposited over the patterned etch stop and then patterned to define the interconnect lines
20
. A single etch process is then performed to define the interconnects down to the etch stop and to etch the unprotected dielectric exposed by the patterned etch stop to define the contacts/vias.
Silicon nitride has been the etch stop material of choice. However, the silicon nitride disposed between the dielectric layers is within the fringing field between the interconnects. Silicon nitride has a relatively high dielectric constant (dielectric constant ~7) compared to the surrounding dielectric, and it has been discovered that the silicon nitride may significantly increase the capacitive coupling between interconnect lines, even when an otherwise low k dielectric material is used as the primary insulator. This may lead to cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the device.
Therefore, there is a need for a process to form a dual damascene with decreased capacitive coupling between interconnects.
SUMMARY OF THE INVENTION
The present invention provides a process sequence and etch stop material which provides a reliable dual damascene structure while minimizing the contribution of the etch stop layer to the capacitive coupling between interconnect lines. In one embodiment, a low k dielectric film, such as an amorphous carbon (&agr;-C) or amorphous fluorinated carbon (&agr;-FC) film is used as the etch stop below an intermetal dielectric (IMD). Other low k materials such as parylene, AF
4
, BCB, PAE, oxynitride and silicon carbide may also be used.
A preferred process sequence of the invention comprises depositing a first dielectric layer, such as a fluorinated silicate glass (FSG) layer, on a substrate, depositing a low k dielectric etch stop, such as an &agr;-FC layer, on the first dielectric layer, patterning the etch stop to define the contacts/vias, depositing a second layer of a dielectric, such as FSG, patterning a resist layer on the second layer of dielectric to define one or more interconnects, and etching the interconnects and contacts/vias. The interconnects are etched down to the etch stop in the final etch step, and then the etching continues past the patterned etch stop to define the contacts/vias. Once the dual damascene structure has been formed, a barrier layer is preferably deposited conformably in the structure prior to filling the structure with copper to isolate the copper from other materials, such as silicon. The upper surface is then planarized using chemical mechanical polishing techniques.


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Tue Nguyen, Bruce D. Ulrich, Lynn R. Allen and David R. Evans, “A Novel Damascene Process for One Mask Via/Interconnect Formation,” 1996 Symposium on VLSI Technology D

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