Method of forming DRAM capacitors with a native oxide etch-stop

Details Method of forming DRAM capacitors with a native oxide etch-stop Method of forming DRAM capacitors with a native oxide etch-stop

1999-12-29

2001-05-29

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000

Reexamination Certificate

active

06238974

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a process of making semiconductor integrated circuit devices and, in particular, to a process of fabricating a semiconductor IC structure for storage of electrical charges. More particularly, this invention relates to a process of fabricating the bottom electrode for a charge storage capacitor for memory IC devices.
2. Description of Related Art
Charged and discharged status of capacitors are used as the basis for the storage of information bits in memory cells of semiconductor DRAM devices. For example, in a particular circuit design, the charged capacitor of a DRAM memory cell may be used to represent a binary data bit of 0, while its discharged status represents 1. Of course the reverse scheme is also allowable.
Capacitance or, in other words, the amount of electric charges held in a capacitor is determined by several factors. These include the surface area of the capacitor electrodes, the electrical isolation between the electrodes, as well as the dielectric constant of the capacitor dielectric material embedded between the electrodes.
To access the information storage content of a particular memory cell of a DRAM device, a field-effect transistor (FET) known as transfer FET is used to couple the target capacitor in the cell to the proper bit line of the memory cell array. The coupling allows the electrical charges to be sensed by transferring to the related circuitry of the supporting logic. In this process, the particular memory array bit line is electrically connected to one of the source/drain terminals of the transfer FET, while one electrode of the cell capacitor is connected to the other of the source/drain terminals of the transfer FET. The corresponding word line for this access is then connected to the gate terminal of the transfer FET. A timely issued gating signal sent via the word line allows the charges accumulated in the capacitor to be transferred for sensing via this established circuit path using the transfer FET as the switching device connecting the capacitor to the supporting logic.
integration densities of IC devices are constantly increased for increasing IC performance. In the case of DRAMs, increasing circuit density increases storage capacity. In general, the ability to pack more memory cells in one single IC chip also helps in reducing the per-bit costs of these semiconductor memory devices, especially when compared with implementing the same amount of memory capacity over a multiple number of IC devices.
Several practices can result in the improvement of IC device integration density. These include the reduction of the size of wiring lines in the circuitry, the size of gate terminal of transistors, as well as the isolation regions reserved between circuit elements. These dimensional reductions are dependent on the improvement over the resolution of design rules for implementing IC devices.
Planarity of IC devices contradicts the requirement that capacitor capacitance of DRAM memory cell units be maintained at an acceptable level while reduction of design rule resolution reduction is also implemented. Insufficient capacitance of memory cell capacitors generates a series of problems for DRAM devices. Due to the inherent nature of capacitors implemented in normal DRAM memory cells, electric charges accumulated in the capacitors leak inevitably as time prolongs. Thus, excessive leakage currents lead to the requirement of higher refresh frequency in DRAM operation. Higher memory cell refresh frequencies, however, consumes directly into the DRAM duty cycle for memory access operation.
On the other hand, a memory cell storage capacitor having an electric voltage across the electrodes decaying at a faster rate due to larger leakage current would place more demands on the charge-sensing amplifier in the memory access circuitry of the device. In other words, the charge sense amplifier must be equipped with a better sensitivity in order to accurately sense and judge the high- or low-status of the voltage of the capacitor.
Thus, as DRAM devices are being manufactured with ever higher fabrication resolutions, various efforts are being employed to increase the storage cell capacitor capacitance. Complex capacitor configurations such as three-dimensional electrode structures are used to increase the electrode surface area in order for the capacitor to hold more electric charges within the same physical three-dimensional space. However, these complex three-dimensional structures are difficult to fabricate, and it will become even more difficult as the memory cells get smaller in size.
Forming hemispherical-grain polysilicon (HSG—Si) over the surface of the electrodes of the storage capacitor is one development recently employed for increasing the capacitor capacitance. Conventional DRAM storage capacitors have traditional planarized polysilicon forming the electrodes. These storage capacitors have basically a flat bottom electrode surface. HSG—Si is a special form of polysilicon exhibiting a coarse surface. When deposited over the surface of the bottom electrode of storage capacitors with a properly controlled procedure, the HSG—Si is capable of effectively increasing the surface area of the capacitor bottom electrode. An increase of roughly 1.8 times the capacitance had been achieved by such an HSG—Si deposition.
However, if an even larger increase of electrode surface area in addition to this simple HSG—Si deposition is desired, three-dimensional surface contours such as pillars, fins, cavities, recesses or similar structural configurations must be formed over the surface of the electrode before the HSG—Si deposition.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a process of fabricating bottom electrode for memory cell capacitor of DRAM devices having greatly increased electrode surface area by providing a generally curved electrode surface in combination with a coarse surface characteristic.
The invention achieves the above-identified object by providing a process of fabricating a structure for storing electrical charges for the bottom electrode in a storage capacitor of the memory cells in a DRAM device. The process includes the steps of forming an insulation layer on the surface of the substrate of the device, and the insulation layer is patterned to form a contact opening exposing a source/drain region of the transistor of the memory cell. A first electrically conductive layer is formed covering the insulation layer and further filling, into the contact opening, with the first electrically conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first electrically conductive layer. A second electrically conductive layer is then formed, and is patterned to form a recess substantially located above the location of the contact opening, formed in the insulation layer. A layer of HSG—Si is formed over the surface of the second electrically conductive layer and the surface of the recess, and the HSG—Si layer and the second electrically conductive layer are subsequently patterned to form the bottom electrode of the capacitor.


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