Method of forming gate electrode with polycide structure in...

Details Method of forming gate electrode with polycide structure in... Method of forming gate electrode with polycide structure in...

1999-12-13

2001-06-19

Smith, Matthew S. (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S528000, C438S264000, C438S585000, C438S592000, C438S683000, C438S652000

Reexamination Certificate

active

06248632

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a gate electrode of a MOSFET, and more particularly to a method of forming a gate electrode with a polycide structure in semiconductor device.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 &mgr;m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysiliocn layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a polycide structure in which a silicide layer using a refractory metal such as tungsten(W) and titanium(Ti) is formed on the polysilicon layer, has been researched.
FIG. 1A
to
FIG. 1C
show a method of forming a gate electrode with a titanium polycide structure in accordance with a prior art.
As shown in
FIG. 1A
, a gate oxide layer
11
is grown on a semiconductor substrate
10
and a doped polysilicon layer
12
deposited thereon.
As shown in
FIG. 1B
, a titanium silicide(TiSi
x
) layer of an amorphous phase is deposited on the polysilicon layer
12
by physical vapor deposition(PVD) using TiSix target. Next, the TiSi
x
layer of the amorphous phase is thermal-treated by rapid thermal processing(RTP) at a selected temperature for several seconds, to be transformed into a titanium silicide(TiSi
2
) layer
13
of a crystalline phase.
As shown in
FIG. 1C
, an oxide(or nitride) layer
14
is formed on the TiSi
2
layer
13
, for a self-aligned contact(SAC) process which will be performed after. The oxide layer
14
, the TiSi
2
layer
13
, the polysilicon layer
12
and the gate oxide layer
11
are patterned by photolithography and etching process to form a gate electrode.
Conventionally several thermal processes such as a first thermal process for gate re-oxidation, a second thermal process for forming source/drain, a third thermal process for planarizing a intermediate insulating layer and a fourth thermal process for forming a capacitor and the like, are performed subsequently, after forming the gate electrode as above described.
FIG. 2
shows a cross sectional view of a gate electrode with a titanium polycide structure in which a TiSi
2
layer
23
is formed on a polysilicon layer
22
according to the prior art. However, when performing above thermal processes respectively, the TiSi
2
layer
23
is agglomerated to generate stress, so that Ti of TiSi
2
layer
23
is diffused into the polysilicon layer
22
and reacted with Si of the polysilicon layer
22
, thereby deteriorating the interface roughness between the polysilicon layer
22
and the TiSi
2
layer
23
(TiSi
2
layer/polysilicon layer), as shown in
FIG. 2
, after performing above thermal processes.
Furthermore, in case the interface roughness is extremely deteriorated, the TiSi
2
layer
23
comes in contact with a gate oxide layer
21
, thereby deteriorating the property of the gate oxide layer
21
. As a result, the reliability of a device is deteriorated.
As not above described, in
FIG. 2
, reference numbers
20
,
24
,
25
and
26
indicate a silicon substrate, a mask oxide layer, a spacer oxide layer and source/drain regions, respectively.
Moreover, although described on the gate electrode with the titanium polycide structure, these problems mostly occur in gate electrode with a polycide structure.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer by preventing a refractory metal of a silicide layer from diffusing into a polysilicon layer when performing thermal processing subsequently, for solving the problems in the conventional art.
To accomplish this above object, in the present invention, a nitrogenous polysilicon layer is formed on the surface of the polysilicon layer, prior to forming the silicide layer, considering the refractory metal diffusing into the polysilicon layer because of the columnar structure of the polysilicon layer.
According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions(N
2
+
) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4833099 (1989-05-01), Woo
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 5393685 (1995-02-01), Yoo et al.
patent: 5429974 (1995-07-01), Hsue et al.
patent: 5508212 (1996-04-01), Wang et al.
patent: 5648287 (1997-07-01), Tsai et al.
patent: 5710454 (1998-01-01), Wu
patent: 5723893 (1998-03-01), Yu et al.
patent: 6069041 (2000-05-01), Tanigami et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 01245560 (1989-09-01), None
patent: 02031427 (1990-02-01), None
patent: 07202011 (1995-08-01), None
patent: 08195358 (1996-07-01), None
patent: 08250451 (1996-09-01), None
patent: 10303422 (1998-11-01), None

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