Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-21
2001-08-28
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S529000, C438S592000
Reexamination Certificate
active
06281086
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices, and, more particularly, to semiconductor devices having a gate electrode with improved electrical characteristics and method of making same.
2. Description of the Related Art
In the field of semiconductor integrated circuit devices, dimensions/sizes of design features are being steadily decreased for a variety of reasons. For example, design feature sizes are being decreased to achieve higher packaging densities for improving device performance, and to improve electrical performance characteristics of the semiconductor devices, such as a field effect transistor.
Complex digital circuits, such as central processing units (CPUs) and the like, demand fast switching transistors. All other things, being equal, the shorter the channel length of a transistor, the faster it will operate. Accordingly, there is a constant drive to reduce the channel-length on modern transistor devices. For example, the longitudinal dimension of a gate conductor of a transistor, i.e., the gate width, may extend to 20 &mgr;m, whereas the distance between the drain and source, ie., the channel length or gate length, may be reduced to 0.2 &mgr;m or below.
As the channel length has been reduced to obtain the desired switching characteristic, the length of the gate electrode has also been reduced. Since the gate electrode may only be electrically connected at one end, the electrical charges used to establish a transverse electrical field for forming the channel between the drain region and the source region of the transistor have to be transported along the entire width of the gate electrode. Given the small transverse dimension (length) of the gate electrode, the electrical resistance is relatively high which may result in higher RC-delay time-constants. Hence, generation of the transverse electrical field used to fully open the channel is delayed, thereby deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is reduced. Thus, the a switching time of the transistor is no longer limited by the drain and source characteristics, but rather significantly depends on the delay associated with signal propagation along the gate electrode, i.e., the transistor performance depends, at least in part, on the resistance of the gate electrode in the longitudinal direction of the gate electrode, i.e., in the gate width direction.
One illustrative prior art device and process for forming a gate electrode, and a conductive layer in contact with the gate electrode of such a device, will be explained with reference to various cross-sectional views of an illustrative MOS transistor in various stages of the fabrication process as depicted in
FIGS. 1A-1D
. As shown in
FIG. 1A
, shallow trenches
2
are formed in a semiconductor substrate
1
to define an active region
30
. Thereafter, a gate dielectric layer
3
consisting of, for example, silicon dioxide (SiO
2
) is formed on the semiconductor substrate
1
between the shallow trenches
2
. A polycrystalline silicon layer (not shown) may then be blanket-deposited over the semiconductor substrate
1
and gate dielectric layer
3
and, subsequently, patterned using traditional photolithography and etching processes to define a gate electrode
4
over the gate dielectric layer
3
. The gate electrode
4
has a top surface
4
A. In this embodiment, the gate dielectric layer
3
is used as an etch stop layer although that is not required.
FIG. 1B
is a cross-sectional view of the illustrative prior art transistor at the stage where a portion of the gate dielectric layer
3
, extending beyond the gate electrode
4
, has been removed by traditional etching processes. Moreover, a plurality of dielectric sidewall spacers
5
have been formed adjacent the gate electrode
4
after a first light-dosage dopant implantation step is performed to form lightly doped source and drain regions
6
, ie., the source/drain extensions. Thereafter, in a further dopant implantation step, highly doped drain and source regions
7
having a surface
7
A are formed. The drain and source regions may also be subjected to a subsequent rapid thermal annealing (RTA) step.
Next, as shown in
FIG. 1C
, a layer
8
comprised of a refractory metal may be blanket-deposited over the structure shown in FIG.
1
B. The layer
8
may be comprised of any suitable refractory metal, such as titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt) or the like. Prior to the formation of the layer
8
, the substrate may be cleaned to remove any residual material, e.g., oxides, from the surfaces
4
A,
7
A of the gate electrode
4
and the drain and source regions
7
. Next, the structure may be subjected to a heating process, e.g., a rapid thermal anneal (RTA) process, at low temperatures to form an initial silicide phase on the surfaces
7
A of the drain and source regions
7
and on the surface
4
A of the gate electrode
4
. Any portion of the metal layer
8
that is not converted into a metal silicide may be removed by selective wet etching. In a further RTA-treatment, at a higher temperature, the silicide formed on the surfaces
4
A,
7
A is transformed into a low ohmic phase to reduce the respective contact resistances. During the process of forming the metal silicide, some portion of the gate conductor
4
and the drain and source regions
7
may be consumed.
FIG. 1D
is a cross-sectional view of the illustrative transistor fabricated as described above with a gate contact silicide
9
formed on the gate electrode
4
, and metal silicide contacts
15
over the drain and source regions
7
. The width of the gate electrode
4
for the transistor shown in
FIG. 1D
may extend for distances to, for example, 20 &mgr;m in the direction perpendicular to the drawing plane of
FIG. 1D
, i.e., into the drawing. An electrical connection with a gate wiring line is usually provided only at one end portion the gate electrode
4
. The resistance of the gate electrode
4
in the gate width directions depends, in part, on the cross-sectional area of the gate contact silicide
9
illustrated in FIG.
1
D. As the length of the gate conductor, i.e., the dimension of the gate electrode in the source-drain-direction, is decreased due to efforts to reduce the size of the transistor and increase its performance, the gate resistance increases linearly, thereby causing deteriorated signal performance.
The present invention is directed to a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems, and a method of making such a device.
SUMMARY OF THE INVENTION
The present invention is generally directed to semiconductor devices having a gate electrode with improved electrical characteristics and a method of making same. In one illustrative embodiment, the method comprises providing a semiconducting substrate, forming a gate electrode above the substrate, the gate electrode having a top surface and a plurality of side surfaces, and forming a metal silicide layer on the top surface of the gate electrode and along at least a portion of the side surfaces of the gate electrode.
One illustrative embodiment of a semiconductor device in accordance with the present invention is comprised of a semiconducting substrate and a gate electrode positioned above the substrate, the gate electrode having a top surface and a plurality of said surfaces. The device further comprises a metal silicide layer positioned above the top surface of the gate electrode and along at least a portion of the side surfaces of the gate electrode, and a plurality of source/drain regions.
REFERENCES:
patent: 5937319 (1999-08-01), Xiang et al.
patent: 5998273 (1999-12-01), Ma et al.
patent: 6017809 (2000-01-01), Inumiya et al.
patent: 6046105 (2000-04-01), Kittl et al.
patent: 6069032 (2000-05-01), Lee
patent: 6074938 (2000-06-01), Asamura
patent: 6093609 (2000-07-01), Chuang
patent: 6121138 (2000-0
Horstmann Manfred
Mantei Tilo
Wieczorek Karsten
Advanced Micro Devices , Inc.
Lebentritt Michael
Williams Morgan & Amerson P.C.
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