Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-23
2001-03-06
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S772000
Reexamination Certificate
active
06197647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to a method of forming a thin gate oxide using a low temperature oxidation followed by an in situ deposition of polysilicon.
2. Description of the Relevant Art
The fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active and isolation regions through an isolation process such as field oxidation or shallow trench isolation. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Next, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into two regions referred to as the source region and the drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions.
As transistor channels shrink below 0.5 microns, the limitations of conventional transistor processing become more apparent. To combat short channel effects in deep sub-micron transistors, the depth of the source/drain junctions and the thickness of the gate oxides must be reduced. Devices become more susceptible, however, to diffusion of electrically active impurities located in the conductive gate structure across the gate oxide and into the active area of the transistor as the gate oxide thickness decreases below 50 angstroms. The presence of these impurities within the channel region can undesirably alter the threshold voltage of the device. This problem is especially acute for boron implanted gate structures. In addition, thinner oxides increase concerns about hot carrier damage and oxide breakdown due, in part, to increased electrical fields within the transistor channel and across the gate dielectric. With respect to the latter, a 3 volt bias applied across a 50 angstrom gate oxide of an MOS transistor results in an electrical field of 6×10
6
V/cm, which is considered to be an upper limit on the electrical field sustainable by a thermally formed SiO
2
film. See, e.g., 1 S. Wolf & R. Tauber,
Silicon Processing for the VLSI
Era 183 (Lattice Press 1986) [hereinafter “Wolf Vol. 1”]. Moreover, “cold” carrier tunneling becomes significant in gate dielectrics thinner than approximately 60 angstroms and, because of these tunneling effects, 30 angstroms has been reported as a lower limit for gate oxide thickness. See 3 S. Wolf,
Silicon Processing for the VLSI
Era438 (Lattice Press 1995) [hereinafter “Wolf Vol. 3”].
In addition to reliability concerns, thin oxides present significant manufacturing challenges as well. The uniformity of the gate dielectric film across the wafer becomes more critical as the film thickness decreases. A 5 angstroms variation in film thickness across a wafer is far more significant in a 50 angstrom film than a 150 angstrom film. Greater control over oxide growth rates and uniformity are needed to insure that the thinner dielectric can be consistently reproduced in a manufacturing environment.
Despite the numerous problems noted, thin gate dielectrics are desirable because the transistor drive current is inversely proportional to the gate oxide thickness over a wide range of operating conditions. Because higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness (as well as other transistor geometries including channel length and junction depth) without significantly reducing the reliability of the integrated circuit. Nitrogen bearing gate dielectrics including oxynitride gate dielectrics have been used to enhance the quality of thin (i.e., less than 100 angstroms) gate oxides and to reduce boron penetration. In Kwong (U.S. Pat. No. 5,397,720), for example, a method of forming an oxynitride gate electric is disclosed. The Kwong method consists essentially of growing an oxynitride layer in an N
2
O ambient and thereafter increasing the nitrogen concentration within the dielectric by introducing heated NH
3
. Similarly, in Cho (U.S. Pat. No. 5,541,141), an oxynitride gate dielectric is grown with a 3-stage process. During the first and third phases, an N
2
O ambient is used. During the second phase, NH
3
is added to the N
2
O mixture to control the oxidation rate and the influx of nitrogen to the oxynitride film. While approaches such as those of Kwong and Cho address some of the reliability issues associated with thin oxides, they do not address the manufacturing variability that prevents the consistent reproduction of high quality, ultra thin dielectric films.
Therefore, it would be highly desirable to fabricate ultra-thin MOS gate dielectrics that exhibited resistance to penetration of mobile carriers such as boron and improved quality characteristics over conventionally formed gate dielectrics with a consistently reproducible and manufacturable process.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface is used to create a thin oxide followed by in situ deposition of polysilicon. The low temperature oxidation in combination with the in situ deposition of polysilicon is capable of advantageously producing an extremely thin gate dielectric having a thickness in the range of approximately 5 to 15 angstroms. Nitrogen is preferably incorporated into the polysilicon to serve as a barrier to migrating impurities.
Broadly speaking, the present invention contemplates a semiconductor process in which a semiconductor substrate is provided. Preferably, the semiconductor substrate includes a p-type epitaxial layer formed on a p+ silicon bulk. Preliminarily, the upper surface of the semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the semiconductor substrate. The formation of the gate dielectric occurs in a first oxidation chamber. A first polysilicon layer is then formed on the gate dielectric layer. The formation of the first polysilicon layer, in the presently preferred embodiment, is accomplished in situ following the formation of the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer.
In a preferred embodiment, the process further includes the steps of forming a polysilicon gate structure using conventional mask and etch techniques and forming a pair of source/drain structures in an upper region of the semiconductor substrate. The source/drain structures are laterally displaced on either side of a channel region of the semiconductor substrate. The channel region is aligned with the polysilicon gate structure. In one embodiment, the cleaning of the semiconductor substrate upper surface includes the steps of immersing the semiconductor substrate in a solution of H
2
O, NH
4
OH, and H
2
O
2
maintained at a temperature in the range of approximately 65° to 80° C. for a duration of approximately 5 to 15 minutes and thereafter immersing the semiconductor substrate into a second solution. The second solution includes H
2
O, HCl, and H
2
O
2
maintained at a temperature in the range of approximately 65° to 80° C. for a duration of approximately 5 to 15 minutes. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O
2
. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300° C. during the formation of the gate dielectri
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Booth Richard
Conley Rose & Tayon PC
Doffer Kevin L.
Kowert Robert C.
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