Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-04
2001-08-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06281064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for providing dual work function doping, and more particularly relates to providing an array of gate structures whereby some of the gate structures are P+ doped and other gate structures are N+ doped. The present invention is especially advantageous for providing structures that include both DRAMs and logic circuits.
2. Description of the Related Art
Over the last several years, significant advances have occurred in increasing the circuit density in integrated circuit chip technology. The ability to provide significantly increased numbers of devices and circuits on an integrated circuit chip has, in turn, created an increased desire to incorporate or integrate additional system functions onto a single integrated circuit chip. In particular, an increasing need exists for joining both memory circuits and logic circuits together on the same integrated circuit chip.
In fabricating dynamic random access memory (DRAM) circuits, the emphasis has been on circuit density along with reduced cost. On the other hand, when fabricating logic circuits, the emphasis has been on creating circuits that operate faster. Accordingly, this desire for dual work function creates additional problems with respect to the complexity and relative cost of the fabricating process. For instance, memory circuits achieve increased density requirements by employing self-aligned contacts (borderless bit line contacts), which are easily implemented in a process having a single type (e.g. typically N+ type) gate work function. A buried-channel P-type metal oxide semiconductor (PMOSFET) is used in creating DRAMs since such permits a single work function gate conductor, N+, to be used throughout the fabrication process. This results in significant cost savings in fabricating DRAMs, but at the expense of creating an inferior performing PMOSFET. On the other hand, logic circuits require both P+ and N+ gated MOSFETs in order to achieve the necessary switching speeds. P+ and N+ gate conductor devices are highly desirable for merged logic and DRAM products.
High-performance logic requires the use of both N+ and P+ doped gate conductors. Although currently practiced high-performance logic processes provide dual workfunction gate conductors, they do not use an insulating gate cap because of density requirements, and hence the need for diffusion contacts borderless to gate conductors, which are of secondary importance to speed. In 13 DRAMs, an insulating cap which is self-aligned to the gate conductor is essential for forming bitline contacts which are borderless to the wordlines. Borderless contacts are needed for achieving the highest density memory cell layouts. However, cost-effective DRAM processes use only a single N+ polysilicon gate conductor. Thus, there is currently no economically attractive process for providing both dual workfunction gate doping and the capability of borderless diffusion contacts.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional techniques, an object of the present invention is to provide dual workfunction doping gate conductors and including a self-aligned insulating gate cap.
It is another object of the present invention to provide dual work function doping. This may include providing a semiconductor substrate, a gate insulator conductor (comprising intrinsic polysilicon and overlying silicide layer) and an insulating cap. The method may also include providing insulating spacers (such as boron silicate glass spacers) along sides of the silicide layer (WSi
x
) and the insulating cap, doping portions of the semiconductor substrate and the conductor with a first conductive type and other portions with a second conductive type, and annealing the conductor such that the dopants of the first and second conductive types spread over the respective conductors.
Portions of the silicide layer and portions of the insulating cap may be etched to form a partial gate conductor stack prior to providing the insulating spacers. After providing the insulating spacers and prior to doping, the method may further include etching the intrinsic conductor at areas of the conductor not covered by the spacer material.
An oxide layer may be formed on portions of the semiconductor substrate not covered with the intrinsic conductor. Insulating spacers may be removed prior to doping portions of the semiconductor substrate and the conductor.
Portions of the semiconductor substrate may correspond to source and drain contact regions. The method may further include extending the source and drain regions in the support region of the substrate to a region at least under the annealed conductor. The method may also include forming source and drain regions in the array regions.
It is also an object of the present invention to achieve the dual work function requirement for selectively applying either P+ or N+ doping to the gate conductor while at the same time creating a self-aligned insulating cap on the gate conductor.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
REFERENCES:
patent: 5937289 (1999-08-01), Bronner et al.
patent: 6051494 (2000-04-01), Iwamatsu et al.
Bronner Gary B.
Divakaruni Ramachandra
Mandelman Jack A.
International Business Machines - Corporation
Lee Calvin
McGinn & Gibb PLLC
Neff, Esq. Daryl K.
Smith Matthew
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