Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reissue Patent
1996-09-12
2001-03-20
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S636000, C438S645000, C438S699000
Reissue Patent
active
RE037104
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to
a
semiconductor fabrication process and more particularly to a process for gate patterning over an active area isolation.
BACKGROUND OF THE INVENTION
During semiconductor fabrication
,
a conventional process starts with a wafer substrate
10
, as depicted in
FIG. 1
, that has patterned thin oxide layers
12
separating isolation regions of thick (or field) oxide
11
. In the process depicted in
FIG. 1
, during exposure and patterning of photoresist
15
via reticle
16
, light can reflect off of the uneven
topology
topography
of silicide
14
and cause what is know as reflective notching. The reflective notching in the photoresist pattern is then transferred into the underlying conductive layer following a subsequent etch.
As seen from the top view of
FIG. 2
, a conductive strip
21
shows the results of reflective notching during the exposure of the photoresist that has caused some of the conductive strip to be removed during the etching of the strip. In this case, the conductive strip
21
has been patterned over active area
22
to serve as a control gate to an MOS device. It becomes obvious that this reflective notch is undesirable as it would reduce the reliability of the MOS device.
The present invention addresses the reflective notching problem by forming a planarized conductor on a wafer's surface that has
a
an
uneven
topology
topography
that results from the formation of
spaced apart
spaced-
apart
, patterned oxide isolation regions including oxide regions formed by LOCOS trench isolation and other advanced isolation technologies.
SUMMARY OF THE INVENTION
The present invention is realized in a process for providing a planarized conductor on a non-planar starting substrate
,
by:
a) forming a first layer of planarized conductive material overlying neighboring isolation regions such that the height of the conductive material extends above the
topology
topography
of the isolation regions; and
b) patterning the first and second conductive material thereby forming the planarized conductor.
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patent: 4966868 (1990-10-01), Murali et al.
patent: 5030584 (1991-07-01), Nakata
patent: 5037772 (1991-08-01), McDonald
patent: 5063175 (1991-11-01), Broadbent
patent: 5069002 (1991-12-01), Sandhu et al.
patent: 5122473 (1992-06-01), Mazzali
patent: 5126289 (1992-06-01), Ziger
patent: 5200030 (1993-04-01), Cho et al.
patent: 5264076 (1993-11-01), Cuthbert et al.
patent: 5302551 (1994-04-01), Itanmanesh et al.
Dennison Charles H.
Doan Trung T.
Britt Trask
Micro)n Technology, Inc.
Powell William
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