Method of forming a flash memory device

Details Method of forming a flash memory device Method of forming a flash memory device

1999-02-01

2001-09-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000

Reexamination Certificate

active

06294428

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87121255, filed Dec. 19, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of forming a memory device, and more particularly, to a method of forming a flash memory device.
2. Description of the Related Art
Flash memory, which is a kind of electrically erasable and programmable read only memory (EEPROM), is currently one the most widely used memory devices applied in personal computers and electronic equipment. A memory cell in a flash memory comprises a transistor with a floating gate to achieve the operations of writing, erasing, and storing data while electrically shut down.
FIG. 1A
is a schematic, cross-sectional view showing a conventional flash memory device. As shown in the figure, a memory region
102
and a peripheral circuit region
104
within a substrate
100
are isolated from each other by an isolating structure
101
. A stacked gate
106
of a flash memory is formed on the memory region
102
. A capacitor
108
of a transistor is formed on the peripheral circuit region
104
. The stacked gate
106
comprises a tunneling oxide layer
110
, a floating gate
112
, a dielectric layer
114
and a control gate
116
. The capacitor
108
comprises a gate oxide layer
118
and a conductive gate layer
120
. A source/drain region
138
is formed in the memory region
102
to complete the flash memory. Another source/drain region
140
is formed in the peripheral circuit region
104
to complete the transistor.
To enhance the reliability of the flash memory, an oxidation step is usually used to partially oxidize the edge of the floating gate
112
above the tunneling oxide layer
110
to form an oxide layer
134
as shown in FIG.
1
B. Forming the oxide layer
134
increases the total thickness of the tunneling oxide layer
110
. However, the capacitor
108
in the peripheral circuit region
104
is exposed in an oxygen environment while performing the oxidation step. The conductive gate layer
120
is oxidized to form an oxide layer
135
above the edge of the gate oxide layer
118
. The oxidation increases the total thickness of the gate oxide layer
118
to decrease a saturated current of the transistor and further to decrease an operation velocity of the flash memory device.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of forming a flash memory device to increase the thickness of the tunneling gate layer of a flash memory cell.
It is another object of the invention to provide a method of forming a flash memory device to keep a saturated current of a peripheral circuit region of the flash memory device and to increase the operation velocity of the flash memory device.
The invention achieves the above-identified objects by providing a method of forming a flash memory device. A substrate at least comprises a memory region and a peripheral circuit region. A stacked gate is formed on the memory region. The stacked gate comprises a tunneling oxide layer, a floating gate and a control gate. A capacitor is formed on the peripheral circuit region. A dielectric layer is formed over the substrate to cover the peripheral circuit region. A thin spacer is formed on the sidewall of the stacked gate. A doped region is formed in the memory region by ion implantation. A thermal process is performed to drive the dopant in the doped region into the substrate and to oxidize a part of the floating gate above the edge of the tunneling oxide layer.
Forming the dielectric layer and the spacer comprises overall formation of a dielectric material on the substrate, providing a mask on the dielectric material positioned on the peripheral circuit region and etching back to form the thin spacer on the stacked gate. The thermal process is performed after forming the stacked gate. The thermal process is a driving-in process performed after any ion implantation step, such as forming source/drain regions or forming doped regions beside the source/drain regions.


REFERENCES:
patent: 4775642 (1988-10-01), Chang et al.
patent: 5940709 (1999-08-01), Chan

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