Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-22
2001-05-22
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S527000, C438S607000
Reexamination Certificate
active
06235568
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a method of forming a novel MOS transistor with deposited silicon regions.
2. Discussion of Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VSLI) circuits, such as microprocessors, memories, and application specific integrated circuits (IC's). Presently, the most advanced IC's are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.25 &mgr;m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 &mgr;m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques and extend beneath gate electrode
102
. Formed adjacent to opposite sides of gate electrode
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain contact regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As device features are continually scaled down, the source/drain contact resistance negatively impacts device performance. In order to help reduce the contact resistance, deposited silicon can be formed on the source/drain contact regions
120
to generate raised source/drain regions and/or to form a sacrificial silicon film for a silicide process. Unfortunately, present techniques for selectively depositing silicon generally require high temperature hydrogen predeposition bakes at 900° C. or higher for a period of a minute or longer. Such high temperature predeposition bakes increase the thermal energy seen by the devices which can cause an undesired redistribution of dopants. Additionally, present selective silicon deposition techniques are highly dependent upon the conductivity type of the silicon surface on which they are formed. As such, one is presently unable to selectively deposit a silicon film onto p-type and n-type silicon surfaces at the same time. Still further, present processing techniques are unable to uniformly deposit highly (>5×10
2
l atoms/cm
3
) insitu doped silicon films at a low temperatures and with a low thermal budget without discontinuities or faceting, making present deposition techniques incompatible with the formation of raised source/drain regions.
Thus, what is desired is a method of forming a selectively deposited, highly conductive insitu doped silicon or silicon alloy film at low temperatures and simultaneously onto both conductivity types of silicon surfaces.
SUMMARY OF THE INVENTION
The present invention describes an MOS device having deposited silicon regions and its method of fabrication. In one embodiment of the present invention a substrate having a thin oxide layer formed on a doped silicon surface is heated and exposed to an ambient comprising germane (GeH
4
) to remove the thin oxide from the silicon surface. A silicon or silicon alloy film can then be deposited onto the silicon surface of the substrate.
REFERENCES:
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patent: 5168072 (1992-12-01), Moslehi
patent: 5252501 (1993-10-01), Moslehi
patent: 5397909 (1995-03-01), Moslehi
patent: 5403434 (1995-04-01), Moslehi
patent: 5716861 (1998-02-01), Moslehi
patent: 5801078 (1998-09-01), Jimenez
patent: 5908309 (1999-06-01), Andoh
patent: 6066523 (1998-06-01), Shim et al.
Suzuki et al., “Effects of Si-Ge buffer layer for low-temperature Si epitaxial growth on Si substrate by rf plasma chemical vapor deposition,” J. App. Phys. 54(3) pp. 1466-1470, Mar. 1983.*
Single-Wafer Integrated Semiconductor Device Processing, Mehrdad M. Moslehi, Member, IEEE, Richars A. Chapman, Member, IEEE, Man Wong, Member, IEEE, Ajit Pranjpe, Habib N. Najm, John Kuehne, Richard L. Yeakley, and Cecil J. Davis. IEEE Transactions on Electron Devices. vol. 39. No. 1. Jan. 1992.
The Viability of GeH4-Based In-situ Clean for Low Temperature Growth Silicon Epitaxial Growth, C.-L. Wang, S. Unnikrishnan, B.-Y. Kim, D.L. Kwong, and A.F. Tasch Microeletronics Research Center, University of Texas at Austin, Autin, TX 78712.
Andideh Ebrahim
Jan Chia-Hong
Murthy Anand
Weldon Kevin
Blakely , Sokoloff, Taylor & Zafman LLP
Booth Richard
Intel Corporation
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