Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-08
2001-01-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S653000
Reexamination Certificate
active
06174797
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of microelectronics fabrications, and more particularly to the field of dielectric layers employed within microelectronics fabrications.
2. Description of the Related Art
In order to fabricate microelectronics devices it is necessary to employ layers of dielectric material to electrically insulate patterned conductor material layers which serve to interconnect the devices in the microelectronics fabrication. As microelectronics devices have become more complex and densely populated, the requirements on the conductor and dielectric layers have become more stringent. The need to minimize power requirements and resistive losses has led to the employment of materials with higher electrical conductivity such as copper, for example. These conductor layers are often fabricated in complex and sophisticated configurations such as inlaid or damascene designs in order to maintain surface planarity in multi-layer structures. The conductor layer may act as a diffusion barrier towards substances emanating from other layers or, conversely, the conductor layer may require a barrier layer to protect it from deleterious substances or to protect other layers from itself.
Dielectric materials which are useful for formation of dielectric layers employed within microelectronics fabrications often are desired to have low dielectric constants to increase circuit performance. Such low dielectric constant materials as organic polymer dielectric materials or fluorine-doped silicon containing glass dielectric materials are commonly employed. Likewise, the increased circuit density and complexity has also led to multiple conductor layers and dielectric layers being fabricated into inter-level metal dielectric (IMD) layers to be able to accommodate all the requirements of increased circuit density and interconnectability. Although methods and materials are available which are satisfactory for these purposes in general, the employment of multi-level conductor layers and low dielectric constant dielectric layers is not without problems.
For example, the dielectric material selected for optimum electrical performance may require a method of formation or a composition which is incompatible with the physical or chemical properties of the conductor material with which the dielectric layer is in intimate contact.
It is thus towards the goal of forming a dielectric layer with an adjacent dielectric diffusion barrier material to protect conductor materials such as copper that the present invention is generally directed.
Various methods have been disclosed for forming conductor layers such as copper and a diffusion barrier layer upon an adjacent dielectric layer to attenuate damage to conductor material from nearby diffusing deleterious species.
For example, Cheung et al., in U.S. Pat. No. 5,785,236, disclose a method for forming aluminum or gold wire bonds to copper bonding pads. The method employs copper bonding pads supported within an interlayer dielectric which may be composed of silicon nitride,
Further, Bhattacharya et al., in U.S. Pat. No. 5,811,870, disclose a method for forming an anti-fuse structure which can be transformed from a non-conductive to a conductive state by application of a voltage across a two-layer insulator. The two-layer structure employs a dielectric layer and an injector layer. The latter employs a silicon-rich silicon oxide or silicon nitride layer.
Yet further, Cleeves et al., in U.S. Pat. No. 5,830,804, disclose a method for forming an encapsulated dielectric layer. The method employs a disposable post material over which is formed a dielectric layer which completely surrounds the post material. A second and third dielectric layer are formed over the encapsulated post and then a portion of the third layer is selectively removed to reveal the disposable post, which is then removed to form an opening in the dielectric layers.
Yet further still, Boeck et al., in U.S. Pat. No. 5,880,018, disclose a method for forming an inter-level metal dielectric (IMD) layer with reduced cross-talk. The method employs a selective placement of a low dielectric constant dielectric material with a dielectric constant equal or less than 3.5 within the IMD layer, and employs various conductor materials.
Finally, Wong et al., in U.S. Pat. No. 5,946,601, disclose a method for forming a layer which can function as a liner or barrier layer to separate a low dielectric constant dielectric layer from surrounding metal layers. The method employs a layer of amorphous hydrogenated carbon nitride and amorphous carbon nitride to separate a low dielectric constant dielectric material containing fluorine from a metal layer.
Desirable in the art of microelectronics fabrication are additional methods for forming an inter-level metal (IMD) layer within which is formed a diffusion barrier dielectric layer and employing conductor layers which are sensitive to corrosion such as copper.
It is towards this goal that the present invention is generally and more specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming upon a substrate employed within a microelectronics fabrication a diffusion barrier dielectric layer intermediate between a dielectric layer and a conductor layer to attenuate inter-diffusion between the dielectric layer and the conductor layer
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the diffusion barrier dielectric layer is formed employing silicon-rich silicon oxide dielectric material deposited employing plasma enhanced chemical vapor deposition (PECVD) upon fluorine-doped low dielectric constant dielectric material.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, where there is formed an inter-level metal dielectric (IMD) layer comprising a layer of fluorine-doped low dielectric constant dielectric material, an intermediate silicon rich silicon oxide dielectric diffusion barrier layer and a copper conductor layer.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention and the third object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming upon a substrate employed within a microelectronics fabrication a dielectric layer, an intermediate diffusion barrier dielectric layer and a conductor layer which constitute an inter-level metal dielectric (IMD) layer with attenuated inter-diffusion. To practice the invention, there is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer and a dielectric layer. There is then formed over the substrate a silicon-rich silicon oxide dielectric layer employing plasma enhanced chemical vapor deposition (PECVD) which acts as a diffusion barrier. There is then formed over the diffusion barrier dielectric layer a copper conductor layer to complete an inter-level metal dielectric (IMD) layer with attenuated inter-diffusion between the dielectric layers and the conductor layer.
The present invention may be applied to substrates employed within microelectronics fabrications including integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, radiation emitting microelectronics fabrications, ceramics substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The present invention uses methods and materials which are known in the art of microelectronics fabrications, but in a novel order and fashion in order to achieve the results of the present invention. Therefore the present invention
Bao Tien-I
Jang Syun-Ming
Ackerman Stephen B.
Dang Phuc T.
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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