Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-03
2001-09-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S243000, C438S244000, C438S245000, C438S246000, C438S247000, C438S249000, C438S386000, C438S387000, C438S388000, C438S389000, C438S390000, C438S391000, C438S392000
Reexamination Certificate
active
06284593
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory cell arrays, and more particular to a process for forming an ultra-scalable hybrid-type memory cell array. Specifically, the present invention is directed to a process of forming a hybrid-type memory cell which is scalable to a minimum feature size, F, of about 60 nm at operating voltages of V
b1h
of about 1.5 V.
BACKGROUND OF THE INVENTION
As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path holes flowing into and out of the portion of the P-well above the buried-strap region.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM memory arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM memory cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM memory cells beyond 110 nm is expected to be limited by floating-well effects.
An illustration of a dominant floating-well dynamic leakage mechanism that limits scalability of prior art vertical DRAM memory arrays is shown in FIG.
1
. Specifically, at a time indicated by point A of FIG.
1
and during a long period of about 5-100 ns of repeated writing of a “1” to other memory cells on the bitline, the P-well of an unselected cell storing a “1” may leak up towards V
b1h
, as the exiting of holes is restricted by parasitic JFET. Leakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo “Floating-Body Effect”.
Insofar as time interval B-C is concerned, the N+ bitline diffusion to P-well barrier is lowered by a downward swing of V
b1h
. Electrons emitted from the bitline diffusion region are collected by the storage node resulting in the formation of a parasitic bipolar transistor, Q
B
, (PW
int
is a floating base) within the memory cell array.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.
An illustration of the storage capacitor voltage vs. the voltage in the portion of the P-well isolated by the depletion region from the buried-strap outdiffusion, as the bitline is cycled, is shown in FIG.
2
. When the bitline is held at V
b1h
, the isolation portion of the P-well leaks up towards the voltage of the adjacent diffusions. With subsequent cycling of the bitline between 0.0 and V
b1h
, the dynamic charge loss mechanism results in charge pumping which discharges the storage capacitor. Between data refresh, greater than 10
6
bitline cycles are possible, which is sufficient to discharge the storage capacitor.
One possible solution to the scalability limitation resulting from floating-well effects, which has not yet been implemented in existing memory structures, includes a contact to the portion of the P-well above the buried-strap outdiffusion region. If such a memory structure is possible, it must be provided in a manner that does not negatively impact cell density, does not degrade junction leakage, and does not add to the fabrication complexity. To date, applicants are unaware of a prior art vertical DRAM memory structure of this type that overcomes the scalability limitation resulting from floating-well effects.
The present invention provides a processing scheme which provides a contacted body and maintains low junction leakage, while actually reducing fabrication cost, retarding the onset of scalability limitations due to floating-well effects to approximately 60 nm groundrules.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process of forming a hybrid memory cell array (6F
2
) which avoids strap-to-strap leakage problems to a minimum feature size, F, of about 60 nm at operating voltages of V
b1h
of about 1.5 V.
Another object of the present invention is to provide a process of forming a hybrid memory cell array wherein the floating-well effects are substantially eliminated.
A further object of the present invention is to provide a process of forming a hybrid memory cell array which has tighter support groundrules.
A still further object of the present invention is to provide a process of forming a hybrid memory cell array in which a low-aspect ratio shallow isolation trench (SIT) region is employed.
A yet further object of the present invention is to provide a process of forming a hybrid memory cell array having improved narrow width effects.
An even further object of the present invention is to provide a process of forming a hybrid memory cell array wherein the spaces between the SIT regions may be greater than 1F without critical overlay in the array.
These and other objects and advantages are achieved by employing the process of the present invention which includes the steps of:
(a) forming at least one deep trench capacitor in a Si-containing substrate, said at least one deep trench capacitor including at least a deep trench polysilicon material, a trench oxide formed on said deep trench polysilicon material, a liner formed on said trench oxide and interior walls of a collar oxide region, and a polysilicon placeholder material formed on said liner;
(b) patterning said polysilicon placeholder material using at least a hardmask to cover a middle portion of said deep trench capacitor and selectively etching exposed portions of said polysilicon placeholder material stopping on said liner;
(c) removing exposed portions of said liner stopping on said trench oxide so as to expose portions of said trench oxide and removing said exposed portions of said trench oxide stopping on said deep trench polysilicon material;
(d) oxidizing any exposed sidewalls and providing a planarized layer of oxide in said etched areas so as to form shallow isolation trench regions which have a depth that is substantially above a buried-strap outdiffusion region to be subsequently formed thereby not cutting into said buried-strap outdiffusion region, yet being deep enough to isolate adjacent bitline diffusion regions to be subsequently formed;
(e) removing said hard mask from said middle portion of the deep trench capacitor, and selectively etching through said remaining polysilicon placeholder material, liner and trench oxide so as to expose a portion of said deep trench polysilicon material;
(f) providing a strap opening in said deep trench capacitor and forming a one-sided buried-strap outdiffusion region through said strap opening, said one-sided buried strap outdiffusion region being confined to a substantially center portion of the deep trench capacitor;
(g) forming bitline diffusion regions about said deep trench capacitor; and
(h) forming a new trench oxide on said exposed portion of said deep trench polysilicon and forming a gate conductor on said trench oxide.
The inventive process further comprises forming wor
Divakaruni Ramachandra
Mandelman Jack A.
Radens Carl J.
International Business Machines - Corporation
Kennedy Jennifer M.
Li Todd M.C.
Scully Scott Murphy & Presser
Tsai Jey
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