Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-02
2001-08-14
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S666000, C438S673000
Reexamination Certificate
active
06274475
ABSTRACT:
TECHNICAL FIELD
The present invention relates to, manufacturing high density, multi-metal layer semiconductor devices with a reliable interconnection pattern and, more particularly, to manufacturing high density multi-metal layer semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers employs a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween.
A second dielectric layer is then applied to fill in the gaps. For example, a dielectric material, such as spin on glass (SOG), is deposited to fill in the gaps between the metal features, and baked at a temperature of about 300° C. to about 350° C., and then cured in a vertical furnace at about 350° C. to about 400° C. for a period of time up to about one hour, depending upon the particular SOG material employed, to effect planarization. Another oxide is deposited by plasma enhanced chemical vapor deposition PEGMD), and the surface is planarized, for example, by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad for the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the bottom surface of the conductive via is in contact with the metal feature.
A conventional conductive via is illustrated in
FIG. 1
, wherein a first metal feature
100
of a first patterned metal layer is formed on first dielectric layer
110
and exposed by a through-hole
120
etched in a second dielectric layer
130
. The first metal feature
100
, which has side surfaces that taper outwardly somewhat due to etching, typically has a composite structure comprising a lower metal layer
102
, e.g., titanium (Ti) or tungsten (W), an intermediate or primary conductive layer
104
, e.g., aluminum (Al) or an Al alloy, and an anti-reflective coating (ARC)
106
, such as titanium nitride (TiN).
Gaps between the first metal feature
100
and another metal feature
190
of the first patterned metal layer are filled with dielectric material
180
, such as SOG or HDP oxide. A dielectric layer
130
, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) or silane, is then former upon the first patterned metal layer, as by PECVD, and planarized, as by CMP.
In accordance with conventional practices, through-hole
120
is formed so that first metal feature
100
completely surrounds the bottom opening, thereby serving as a landing pad for the metal plug filling the through-hole
120
to form the conductive via
160
. The conductive via
160
electrically connects the first metal feature
100
and a second metal feature
140
, which is part of a second patterned metal layer.
The second metal feature
140
is also typically a composite structure comprising a lower metal layer
142
, a primary conductive layer
144
, and an ARC
146
. The plug filling the through-hole
120
to form the conductive via
160
is typically formed as a composite comprising a first adhesion promoting layer
150
, which is typically a refractory material, such as TiN, Ti—W, or Ti—TiN, and a primary plug filling metal
170
such as W. Metal features
100
and
140
typically comprise metal lines with interwiring spacings therebetween conventionally filled with dielectric material
180
, such as SOG or HDP oxide.
The reduction of design features to the range of 0.25 microns and under requires extremely high densification. The conventional practice of forming a landing pad enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height to width of the through-hole. Accordingly, conventional remedial techniques comprise purposely widening the through-hole to decrease the aspect ratio. As a result, misalignment may occur wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a “borderless via”, which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a misaligned through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate, thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate causing a short. Referring to
FIG. 2
, first dielectric layer
210
is formed on a substrate (not shown) and a first metal pattern comprising a first metal feature
200
, e.g. a metal line, comprising anti-reflective coating
206
, is formed on first dielectric layer
210
. Gaps, such as the gap between the first metal feature
200
and another metal feature
290
, are filled with SOG
280
. Dielectric layer
230
is then deposited and a misaligned through-hole
220
formed therein exposing a portion of the upper surface and at least a portion of a side surface of first metal feature
200
, and penetrating into and exposing a portion of SOG layer
280
. Upon filling the through-hole
220
with a metallic plug
260
, typically comprising an initial barrier layer
250
and tungsten
270
, a spike
222
is formed.
Alternatively, SOG may be replaced by hydrogen silsesquioxane (HSQ), which offers several advantages. HSQ is relatively carbon free, thereby avoiding poison via problems and the need to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. Moreover, HSQ has a relatively low dielectric constant, between 3.0 and 4.0 at 1 Mhz, compared to about 4.9 for plasma deposited SiO
2
. A lower dielectric constant reduces parasitic, interline capacitive coupling, thereby increasing circuit speed.
HSQ, however, is susceptible to degradation during processing leading to various problems, including an increase in its dielectric constant. HSQ typically contains between about 70% and about 90% Si—H bonds. Upon exposure to an O
Advanced Micro Devices , Inc.
Quach T. N.
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