Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-20
2001-09-04
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S660000, C438S663000, C438S664000
Reexamination Certificate
active
06284611
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method of performing a self-aligned silicide process using a titanium layer with an overlying titanium nitride barrier layer to prevent nitridation of the titanium layer during the first rapid thermal anneal step, thereby reducing the sheet resistance of the N+ source and drain regions and the N+ polysilicon.
2) Description of the Prior Art
The use of self-aligned silicide (SALICIDE) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, sheet resistance (Rs) at the salicide interface is a key limitation of current SALICIDE processes, particularly as processing speed increases.
In current SALICIDE processes, a titanium layer is deposited over a gate and adjacent source and drain regions. The substrate is then exposed to a rapid thermal anneal (RTA) in which the titanium in areas that overlie silicon (i.e. gate electrode and source and drain regions) reacts with the silicon to form titanium silicide, and the titanium in areas that do not overlie silicon (i.e. nitride or oxide spacers and isolation structures) the titanium does not react. Unreacted titanium is then removed using a selective metal etch. Then a second RTA is performed to further lower the sheet resistance of the silicide.
The RTA steps are performed in a nitrogen containing atmosphere. During the first RTA step, the nitrogen reacts with the titanium at the surface of the titanium layer forming titanium nitride. Thus, the titanium which reacts with nitrogen is not available to form titanium silicide, and the titanium nitride prevents subsequent ion mixing step from effectively reducing the sheet resistance at the silicide interface.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,835,112 (Pfiester et al.) shows a salicide process using a Ge ion implant.
U.S. Pat. No. 4,551,908 (Nagasawa et al.) recites a salicide process with an ion mixing step.
U.S. Pat. No. 5,789,318 (Delfino et al.) shows a salicide process using a sputter deposited TiH
x≦2
which is converted to C-49 TiSi
2
and TiN during a first rapid thermal anneal.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating self-aligned silicide using a titanium nitride barrier layer over a titanium layer to prevent nitridation of the titanium layer during rapid thermal anneal.
It is another object of the present invention to provide a method for forming a self-aligned silicide source and drain contacts and gate contacts while maintaining low sheet resistance in the N+ source and drain regions and the N+ polysilicon.
It is yet another object of the present invention to provide a method for forming a self-aligned with reduced variation of the sheet resistance in the N+ source and drain regions and the N+ polysilicon.
To accomplish the above objectives, the present invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an underlying titanium layer during rapid thermal anneal. The process begins by providing a substrate structure having a gate thereon. A titanium layer is deposited over the substrate structure and the gate. A blanket implant of mixing ions is performed. A titanium nitride barrier layer is deposited on the titanium layer. The substrate structure is rapid thermal annealed causing the titanium layer to react with the underlying silicon to form silicide. The substrate structure is selectively etched to remove the titanium nitride barrier layer and unreacted titanium. A second rapid thermal anneal is performed.
The present invention provides considerable improvement over the prior art. Sheet resistance for N+ source and drain regions is reduced dramatically by the present invention down to a mean of about 5.603 &OHgr;/□ with a standard deviation of about 0.267 &OHgr;/□ for 2 micrometer structures and a mean of about 19.48 &OHgr;/□ with a standard deviation of 2.103 &OHgr;/□ for 0.3 micrometer structures. Sheet resistance for N+ polysilicon regions is reduced by the present invention down to a mean of about 6.54 &OHgr;/□ with a standard deviation of about 0.896 &OHgr;/□.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4551908 (1985-11-01), Nagasawa et al.
patent: 4558507 (1985-12-01), Okabayashi et al.
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 5196360 (1993-03-01), Doan et al.
patent: 5401674 (1995-03-01), Anjum et al.
patent: 5413957 (1995-05-01), Byun
patent: 5789318 (1998-08-01), Delfino et al.
patent: 5831335 (1998-11-01), Miyamoto
patent: 5858846 (1999-01-01), Tsai et al.
patent: 6008111 (1999-12-01), Fushida et al.
patent: 6022795 (2000-02-01), Chen et al.
patent: 6072222 (2000-06-01), Nistler
patent: 6096638 (2000-08-01), Matsubara
Chang Tzong-Sheng
Chou Chen-Cheng
Tien Bor-Zen
Yue Wen-Jye
Ackerman Stephen B.
Pham Long
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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