Method to form bottom electrode of capacitor

Details Method to form bottom electrode of capacitor Method to form bottom electrode of capacitor

1998-12-08

2001-01-23

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S255000, C438S398000, C438S578000, C438S766000

Reexamination Certificate

active

06177326

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices. More particularly the present invention relates to a method for fabricating a bottom electrode of a capacitor.
2. Description of the Related Art
As long as the trend for forming highly integrated circuits continues, methods capable of forming devices having smaller dimensions must be developed. Semiconductor devices having sub-micron line width are currently being manufactured. In the past, the means of increasing the packing density of integrated circuit devices has included the reduction of their structural dimensions. For a DRAM capacitor, that means a reduction of the surface area of its electrode. However, the amount of electric charge that can be stored in the capacitor is greatly reduced.
In general, the amount of stored charge within a DRAM capacitor must be above a certain threshold level so that the stored data can be retrieved correctly. When some of the dimensions of a DRAM capacitor are reduced, the maximum amount of charge the capacitor is capable of storing drops correspondingly. Furthermore, as the charge-storing capacity of the capacitor drops the frequency of refreshes necessary to compensate for the charges lost due to current leakage must be increased. Constant refreshes compromises the data processing speed of the DRAM. Hence, a method to reduce the area occupied by a capacitor on a semiconductor substrate without decreasing its storage capacity is a major issue for design engineers.
One solution to the charge storage problem of a DRAM capacitor is to grow hemispherical-grain silicon on the silicon surface of the bottom electrode. Given two capacitors formed using the same materials and having the same distance of separation between upper and bottom electrodes, the capacitor with hemispherical-grain silicon formed on its bottom electrode can have twice the capacitance of the one without hemispherical-grain silicon.
FIGS. 1A through 1C
are schematic, cross-sectional diagrams used to depict steps in conventional method for fabricating a bottom electrode.
Referring to
FIG. 1A
, a substrate
100
having a MOS
102
is provided. A dielectric layer
104
is formed on the substrate
100
. A via hole
106
is formed in the dielectric layer
104
to expose a source/drain region
103
. A patterned, doped polysilicon layer
108
is formed on the dielectric layer
104
and fills the via hole
106
, wherein the cross-section of the doped polysilicon layer
108
that lies on and above the top surface of the dielectric layer
104
is quadrangular. The source/drain region
103
is connected to the doped polysilicon layer
108
. An ion implantation process
110
is performed.
Referring to
FIG. 1B
, a portion of the surface of the doped polysilicon layer
108
is transformed to an amorphous silicon layer
108
a
and the residue of the doped polysilicon layer
108
is remained as a doped polysilicon layer
108
b.
Because the integration of semiconductors is increased, distance
111
between the doped polysilicon layer
108
becomes smaller. During the ion implantation process
110
, the doped polysilicon layer
108
is shielded by other parts of the doped polysilicon layer
108
or other devices even though the angle of implantation is tilted. As the cross-section of the doped polysilicon layer
108
is quadrangular, the shielding effect is especially obvious. Thus, it is difficult to transform the entire surface of the doped polysilicon layer
108
into the amorphous silicon layer
108
a
. Referring to
FIG. 1C
, a hemispherical-grain layer
112
is formed on the amorphous silicon layer
108
a
. A bottom electrode is made of the doped polysilicon layer
108
b
, the amorphous silicon layer
108
a
and the hemispherical-grain layer
112
.
Since not all the surface of the doped polysilicon layer
108
is transformed to the amorphous silicon layer
108
a
, just a portion of the surface of the bottom electrode is covered by the the hemispherical-grain layer
112
, so that the surface area of the bottom electrode is not sufficiently increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for fabricating a bottom electrode whose cross-section is arced or polygonal to avoid the shielding effect that occurs during the implantation process.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a bottom electrode. The method for fabricating this bottom electrode includes the following steps. A dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned, doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed to an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5240874 (1993-08-01), Roberts
patent: 5773342 (1998-06-01), Fukase
patent: 5821157 (1998-10-01), Lee et al.
patent: 5831282 (1998-11-01), Nuttall
patent: 6013549 (2000-01-01), Han et al.

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