Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-18
2001-05-29
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S297000, C257S379000, C257S381000, C257S382000, C257S383000, C257S385000, C257S389000, C257S903000
Reexamination Certificate
active
06239458
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to a method of manufacturing forming a via structure in a MOSFET Static Random Access Memory (SRAM) cell and the device manufactured thereby.
2. Description of Related Art
U.S. Pat. No. 5,521,113 of Hsue et al. for “Process for Forming a Butting Contact Through a Gate Electrode” shows a method for forming a butting contact through a gate electrode. However, Hsue et al does not show a butt contact between the second and third polysilicon layers.
U.S. Pat. No. 5,422,499 of Manning for “Sixteen Megabit Static Random Access Memory (SRAM) Cell” shows an SRAM cell with a second layer of polysilicon extending over co-planar surfaces in contact with the third polysilicon region that establishes a contact between the TFT drain and the pull down transistor. However, Manning differs from the invention in the configuration of the butting contacts.
U.S. Pat. No. 5,547,892 of Wuu et al. for “Process for Forming Stacked Contacts and Metal Contacts on Static Random Access Memory Having Thin Film Transistors” shows a process for forming a stacked contact for an SRAM device.
As the design rules are reduced for high density memories, the trend is to use the shallow trench isolation process to replace the well known LOCOS (LOCal Oxidation of Silicon) process. A polysilicon via (or Butt-contact structure) has been used for SRAM cell designs. But that approach is hampered by the problem of butt-contact short-circuits to the P-well of a device due to misalignment of the polysilicon gate to active regions or polysilicon_via (or butt-contact) misalignment to the active region.
In the past the VLSI manufacturing process, a problem has existed in that the area of source/drain regions could not be minimized because it was necessary to align the contact hole with the source/drain regions by using a separate masking step and an extra area had to be allocated to compensate for the probability of misalignment.
SUMMARY OF THE INVENTION
The problems solved by this invention are first that it provides for immunity of a polysilicon_via (or butt contact) from being short-circuited to the P-well.
Secondly, this invention minimizes the area of a polysilicon Via relative to the rules. For example, active region extension to the butt contact and the first polysilicon layer extension to the polysilicon via are provided by this invention.
In accordance with this invention, a method is provided for forming an SRAM transistor cell on a doped semiconductor substrate which includes the following steps.
Form buried contact areas in a well in the substrate, a first conductor layer on the well; and a hard silicon oxide mask layer over the first conductor layer.
Define gate conductors from the first conductor layer.
Form lightly doped source/drain regions in the well, form spacers in the well, form source/drain regions in the well and form a first inter-conductor dielectric layer on the cell.
Define a self-aligned contact region in the cell above at least one of the source/drain regions.
Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region, form a second inter-conductor dielectric layer on the cell.
Form a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.
Form the self-aligned contact regions to a source region and a drain region with an interconnection to the buried contact.
The first conductor layer comprises a layer selected from the group of polysilicon and polysilicon/polycide.
The second conductor layer comprises a lamination of polysilicon and tungsten silicide.
The hard silicon oxide mask layer is composed of a material formed from the group consisting of PETEOS and LPTEOS.
The first inter-conductor dielectric layer is composed of a material formed from the group consisting of LPTEOS and PETEOS.
The second inter-conductor dielectric layer is composed of a material formed from the group consisting of LPTEOS and PETEOS.
In accordance with another aspect of the invention, form an SRAM transistor cell on a well in a semiconductor substrate thereof by the steps as starting by forming a gate oxide layer over the well. Form a split polysilicon layer over the gate oxide layer; form buried contact areas in a well in the substrate etching away portions of the split polysilicon layer and the gate oxide layer; and form buried contact regions in the well.
Deposit a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer.
Pattern the lower conductor layer into a gate conductor electrode.
Perform LDD photolithography and ion implant LDD regions into the well adjacent to the gate conductor electrode.
Form spacers adjacent to the gate conductor electrode.
Perform source/drain photolithography and ion implanting.
Form a first inter-conductor dielectric layer on the cell.
Define a self-aligned contact region in the cell above at least one of the source/drain regions.
Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region.
Form a second inter-conductor dielectric layer on the cell.
Form a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.
Form the self-aligned contact regions to a source region and a drain region with an interconnection to the buried contact.
The first conductor layer comprises a layer selected from the group of polysilicon and polysilicon/polycide. The second conductor layer comprises a lamination of polysilicon and tungsten silicide.
The hard silicon oxide mask layer is composed of a material formed from the group consisting of PETEOS and LPTEOS.
The first inter-conductor dielectric layer is composed of a material formed from the group consisting of LPTEOS and PETEOS.
The second inter-conductor dielectric layer is composed of a material formed from the group consisting of LPTEOS and PETEOS.
In accordance with another aspect of this invention, a method of forming an SRAM transistor cell on a doped semiconductor substrate includes the following steps.
Form a gate oxide layer over the substrate.
Form a split polysilicon layer on the gate oxide layer.
Form buried contact areas in a well in the substrate etching away portions of the split polysilicon layer and the gate oxide layer.
Form a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer over the split polysilicon layer and reaching down into contact with the substrate in the buried contact areas.
Form a hard silicon oxide mask layer over the first conductor layer.
Define gate conductors from the first conductor layer.
Form lightly doped source/drain regions in the well.
Form spacers in the well.
Form source/drain regions in the well.
Form a first inter-conductor dielectric layer on the cell.
Define a self-aligned contact region in the cell above at least one of the source/drain regions.
Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region.
Form a second inter-conductor dielectric layer on the cell.
Form a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.
Form a first pass transistor and a second pass transistor, each having a source region, a drain region and a gate conductor.
Form a first pull-down transistor and a second pull-down transistor each having a source region, a drain region and a gate conductor.
Form a first node and a second node.
Form a first load resistor having one end connected to the first node and the other end thereof connected to the power supply connection.
Form a second load resistor having one end connected to the second
Lee Jin-Yuan
Liaw Jhon-Jhy
Ackerman Stephen B.
Jones II Graham S.
Lee Eddie C.
Ortiz Edgardo
Saile George O.
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