Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-02
2001-04-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S253000, C438S254000, C438S003000, C438S396000, C438S397000, C438S652000, C438S654000, C438S655000, C438S666000, C438S667000, C438S608000, C438S686000
Reexamination Certificate
active
06218296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing such a device. More particularly, the present invention relates to a semiconductor device having a pillar-shaped capacitor storage node having a high dielectric film and a method for manufacturing such a device.
2. Background of the Invention
Conventional dynamic random access memory (DRAM) devices include storage nodes, which storage nodes typically include a capacitor. As DRAM devices are scaled down to a line width dimension of about a quarter micrometer, two-dimensional areas occupied by the capacitor become smaller and smaller. Despite reduced cell areas, capacitors require a minimum level of capacitance of about 25 fF to 30 fF. Many methods have therefore been developed to maintain a desired capacitance from decreased two-dimensional areas.
One approach is to increase the height of the capacitor so as to increase the available cell surface areas. The increase in the height of the capacitor at the cell array region, however, causes a large step between the cell array region and peripheral region, thus making it difficult to form metal interconnections.
An alternative approach is to increase the dielectric constant of the dielectric film of the capacitor. Recently, high dielectric materials such as strontium titanate (SrTiO
3
), barium-strontium titanate ((Ba•St)TiO
3
), and the like, having a dielectric constant of more than 10,000, have been adopted as a dielectric film instead of the conventional silicon nitride (Si
3
N
4
) and tantalum oxide (Ta
2
O
5
). However, when the polysilicon is used as a capacitor storage node, a layer of low dielectric characteristics, such as SiO
2
(silicon oxide layer) is formed at the interface between the polysilicon layer and the high dielectric film, thereby increasing the leakage current of the high dielectric film.
Accordingly, there is a need for a storage node that is compatible with high dielectric materials, but which does not degrade the high dielectric characteristics. Because platinum is unreactive with a high dielectric layer during deposition and post-deposition annealing of the high dielectric layer, platinum has been employed as a capacitor storage node when the dielectric film is comprised of a high dielectric material, such as strontium titanate and barium-strontium titanate. However, there are some problems associated with the use of platinum in highly integrated circuit devices. For example, when applied to a process for forming a storage node with about 0.1 to 0.2 micrometers spacing, etched platinum is left on the sidewalls of the patterned storage node. This may occur because it is difficult to form volatile etching by-products during dry etching of the platinum, and so etching by-products remain. As a result, the final storage node has a sloped sidewall profile, and such a sidewall profile can be a serious obstacle to achieving fine pattern size. Also, in severe cases, an electrical bridge may arise between adjacent storage nodes.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there is provided a semiconductor device that includes a pillar-shaped capacitor storage node of a capacitor with a substantially vertical sidewall profile. The pillar-shaped storage node is made of a first barrier metal layer, a first thick conductive layer formed on the first barrier metal layer, a second barrier metal layer formed on the first conductive layer, a second thin conductive layer formed on the second barrier metal layer, a barrier metal spacer formed on both sidewalls of the pillar-shaped storage node, and a conductive spacer formed on both sidewalls of the barrier metal spacer.
According to one feature of the invention, the first thick conductive layer is made of a material that is easily etched by anisotropic dry etching. Preferably, titanium nitride layer and polysilicon may be formed thickly to increase available surface area.
According to another feature of the invention, the second thin conductive layer is made of a transition metal that is unreactive with a later-formed high dielectric material. This transition metal is advantageously formed thinly so as to prevent the formation of an electrical bridge between adjacent storage nodes. The first barrier layer prevents reaction between a polysilicon plug and the first thick conductive layer. The second barrier layer prevents reaction between the first conductive layer and second conductive layer and thereby prevents oxidation of the first conductive layer.
Preferably, the first and second barrier metals are made of a material selected from the group consisting of TiN, TiAlN, TiSiN, TaSiN, TaAlN, ruthenium oxide, iridium oxide, lanthanum strontium cobalt oxide, and a conductive oxide of barium, strontium or ruthenium. Preferably, the thin second conductive layer is made of a material selected from the group consisting of polysilicon, ruthenium and a titanium nitride layer. Preferably, the second conductive layer is made of a material selected from a group consisting of ruthenium, platinum, iridium oxide, ruthenium oxide, lanthanum strontium cobalt oxide, and a conductive oxide of barium, strontium or ruthenium.
Sidewall spacers are provided to protect already-formed layers during subsequent high dielectric deposition and following various heat treatment.
More specifically, the pillar-shaped storage node is formed by the following process sequence. First, a transistor is formed on an active region of a semiconductor substrate. The active region is surrounded by an insulator, i.e., field oxide layer. An insulating layer is formed on the resulting structure. Contact is opened in the insulating layer to a desired portion of the active region. A conductive material such as polysilicon is deposited in the contact opening and on the insulating layer and then planarized to form a polysilicon contact plug therein.
In accordance with another aspect of the invention, there is provided a method of manufacturing such a semiconductor device. In accordance with this method, a first barrier metal layer is formed on the insulating layer and on the polysilicon plug. The first barrier layer serves to prevent reaction between the polysilicon plug and later-formed conductive layers. A first conductive layer is deposed on the first barrier metal layer. The first conductive layer is formed thickly to increase available surface area which is directly related to the capacitance. A conductive material that is easily etched through anisotropic dry etching is selected as such. Preferably, polysilicon or titanium nitride layer may be formed to a thickness of about 1,000 Å to 10,000 Å.
A second barrier layer is formed on the first conductive layer to a thickness of about 100 Å to 1,000 Å. A second conductive layer is then formed on the second barrier metal layer. The second conductive layer is made of a material that is unreactive with later-formed high dielectric materials. Preferably, the second conductive layer is made of a material selected from the group consisting of ruthenium, platinum, iridium oxide, ruthenium oxide, lanthanum strontium cobalt oxide, and a conductive oxide of barium, strontium or ruthenium. The second-conductive layer is formed thinly, preferably, to a thickness of about 100Å to 1,000Å in order to avoid slope etch thereof during anisotropic dry etching.
Using a storage node forming mask, selected portions of the stacked layers are anisotropically etched to form a pillar-shaped storage node. Since the second conductive layer is formed thinly, slope etching thereof can be avoided, thereby forming sidewalls having substantial vertical profiles. Moreover, the first conductive layer that is easily etched is formed thickly and thus advantageously increases available surface of the storage node.
To protect the exposed sidewalls of the first conductive layer
Chung Tae-Young
Hwang Yoo-Sang
Kwak Dong-Hwa
Kennedy Jennifer M.
Niebling John F.
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee, PLLC
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