Method to reduce parasitic capacitance

Details Method to reduce parasitic capacitance Method to reduce parasitic capacitance

1999-09-13

2001-05-29

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S422000, C438S595000

Reexamination Certificate

active

06238987

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fabrication method for an integrated circuit. More particularly, the invention relates to a fabrication method for a metal-oxide-semiconductor field-effect transistor (MOSFET).
2. Description of the Related Art
In the current fabrication of an integrated circuit, a dielectric layer is formed as a device isolation structure to cover the substrate and the transistor after the completion of the manufacturing of the transistor. A consequence of having multiple layers of conductive structure separated by a dielectric material, however, is the formation of a parasitic capacitor between the transistor gate and the source/drain region. The parasitic capacitance between the conductive material separated by the insulating material in microelectronic devices contributes to effects such as the RC delay time and a decrease of the device operating speed.
The capacitance of the parasitic capacitor is related to the dielectric material used between the gate and the source/drain region. The dielectric material between the gate and the source/drain region is normally the material used for the dielectric layer and the spacer to isolate devices. The material for the dielectric layer is typically silicon dioxide (SiO
2
), and for the spacer it is normally silicon dioxide or silicon nitride (Si
3
N
4
). The dielectric constant for these two types of materials are very high (silicon oxide is 3.9, and silicon nitride is 7.0). As a result, the parasitic capacitance presents between the gate electrode and the source/drain region is very high and the device operating speed is adversely affected.
SUMMARY OF THE INVENTION
In the light of the foregoing, the present invention provides a method to lower the parasitic capacitance, which can effectively lower the parasitic capacitance present between the transistor gate and the source/drain region. The RC time delay thereby is decreased and the operating speed of the device is increased.
The present invention provides a method to lower the parasitic capacitance by forming a low dielectric constant air-gap in the dielectric layer at the two sides of the gate. The method in forming the air-gap includes providing a semiconductor substrate with a gate oxide layer. A gate is then formed on the gate oxide layer. A lightly doped drain region is also formed in the substrate at the two sides of the gate. Thereafter, a conformal liner oxide layer is formed on the substrate, followed by forming spacers right next to the liner oxide layer at the two sides of the gate. The spacers are, for example, silicon nitride. A source/drain region connected to the lightly doped drain region is formed in the substrate outside of the spacers. A first dielectric layer is further formed on the substrate, wherein the height of the first dielectric layer is slightly lower than the top of the spacers, thereby partially exposing the surface of the spacers. The spacers are removed by wet etching to form a hole between the gate and the dielectric layer, with the top of the hole narrower than the bottom of the hole. After which, a second dielectric layer is formed by thin film deposition with a weaker step coverage capability to encapsulate the hole and to cover the substrate. In this step, although a part of the second dielectric layer fills the hole, the hole is not completely packed by the second dielectric layer. As a result, the second dielectric layer formed contains an air-gap.
The air-gaps formed in the above method are filled with air. Since the dielectric constant of air is very low (about
1
), the dielectric constant of the dielectric material between the gate and the source/drain region is thereby decreased to effectively reduce the parasitic capacitance.
A main feature of the present invention is an air-gap similar to a spacer is formed at the two sides of the gate, taking the advantage of the low dielectric constant of air to lower the parasitic capacitance between the gate and the source/drain region.
Another feature of the present invention is to form a first dielectric layer having a height slightly lower than the top of the spacers. The spacers are then removed to form a hole. A thin film deposition with a poor step coverage capability is further conducted to form the second dielectric layer encapsulating the hole but not densely packing the hole. An air-gap similar to a spacer is therefore formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5661049 (1997-08-01), Lur et al.
patent: 5736446 (1998-04-01), Wu
patent: 5915182 (1999-06-01), Wu
patent: 5972761 (1999-10-01), Wu

Affiliated with

Also associated with

Rating

Method to reduce parasitic capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to reduce parasitic capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to reduce parasitic capacitance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2460589