Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-12-07
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S597000, C438S706000, C438S707000, C438S714000
Reexamination Certificate
active
06214742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of manufacturing semiconductor devices and more specifically, this invention relates to a method of manufacturing semiconductor devices in which a layer of TiN formed on a surface of metal structures is etched down to the surface of the underlying metal structure.
2. Discussion of the Related Art
In many of the current semiconductor manufacturing processes, the via etch process consists of etching a layer of interlayer dielectric (ILD) and stopping on an ARC (anti-reflection coating) layer, typically consisting of TiN, on top of underlying metal structures, such as interconnects formed from aluminum. The ARC layer is partially consumed during the etch process. After via clean, a barrier layer consisting of TiN or Ti/TiN is formed on the surfaces of the via before filling the via with tungsten. The result is that there exists a significant thickness (the remaining ARC layer and the deposited barrier layer) of relatively high resistance TiN between the overlying metal (usually tungsten) and the underlying metal (usually aluminum). In other current semiconductor manufacturing processes, the via etch process continues through the TiN layer and into the underlying metal, however, this process results in particles of residual metal adhering to the walls of the etched holes in the layer of interlayer dielectric.
FIGS. 1A-1D
show a prior art method of manufacturing a semiconductor device in which a portion of a layer of TiN formed on a metal structure is etched during an etch process to etch the overlying ILD layer.
FIG. 1A
shows a partially completed semiconductor device
100
. The partially completed semiconductor device
100
includes a layer of material
102
that is typically a layer of an interlayer dielectric (ILD) formed from a material such as silicon dioxide. The next layer is known as a metal layer that is patterned and etched to form metal structures such as the one shown at
104
. The metal structure could be a wire that connects one portion of the semiconductor device
100
to another portion of the semiconductor device
100
. Alternatively, the metal structure
104
could be a via that connects a first layer with either a layer underlying the first layer or a layer overlying the first layer. A via
106
that could be formed underneath the metal structure
104
is shown in dashed outline. During the formation of the metal structure
104
and before an ILD layer
108
is deposited, a layer
110
of a material such as TiN is formed on the surface of the metal structure
104
. After the ILD layer
108
is formed, a layer
112
of photoresist is formed on the surface of the ILD layer
108
.
FIG. 1B
shows the partially completed semiconductor device
100
as shown in
FIG. 1A
with the layer
112
of photoresist patterned and developed to form a hole
114
in the layer of photoresist that exposes a selected portion of the ILD layer
108
.
FIG. 1C
shows the partially completed semiconductor device
100
as shown in
FIG. 1B
after an etch process that etches the ILD layer
108
and a portion of the layer
110
of TiN. Note that the etch process is stopped before the etch reaches the metal structure
104
. The etch process is stopped before the etch reaches the metal structure
104
because it has been found that etching the underlying metal causes residue particles to be deposited on the walls of the etched hole. These residue particles cause difficulties with the forming of the barrier layer and the subsequent filling of the hole with a conductive material. However, although the layer of TiN
110
is conductive, the film resistivity of TiN is relatively larger than that of the resistivity of aluminum and tungsten which typically are the metals on either side of the layer of TiN
110
. It is desirable that the layer of TiN
110
be removed entirely to reduce the resistivity of the structure. It is further desirable that the layer of TiN be removed without invading the metal structure
104
underlying the layer of TiN
110
.
FIG. 1D
shows the partially completed semiconductor device
100
as shown in
FIG. 1C
with a thin barrier layer
116
formed on the surfaces of the hole
114
. The barrier layer
116
is typically formed from a material such as TiN, Ti, TaN and TiW or combinations of these materials. After the thin barrier layer
116
is formed, the hole
114
is filled with a conductive material
118
such as aluminum or tungsten. As is known in the semiconductor manufacturing art, the hole
114
is typically filled by forming a blanket layer of the conductive material over the surface of the partially semiconductor device
100
and removing the excess material by a process such as a chemical mechanical polishing (CMP) process.
FIGS. 2A-2E
show a prior art method of manufacturing a semiconductor device in which the layer of TiN formed on a metal structure is etched through by the etch process and the etch process etches part of the underlying metal structure.
FIG. 2A
shows a partially completed semiconductor device
200
. The partially completed semiconductor device
200
includes a layer of material
202
that is typically a layer of an interlayer dielectric (ILD) formed from a material such as silicon dioxide. The next layer is known as a metal layer that is patterned and etched to form metal structures such as the one shown at
204
. The metal structure could be a wire that connects one portion of the semiconductor device
200
with another portion of the semiconductor device
200
. Alternatively, the metal structure
204
could be a via that connects a first layer with either a layer underlying the first layer or a layer overlying the first layer. A via
206
that could be formed underneath the metal structure
204
is shown in dashed outline. During the formation of the metal structure
204
and before an ILD layer
208
is deposited, a layer
210
of material such as a TiN is formed on the surface of the metal structure
204
. After the ILD layer
208
is formed, a layer
212
of photoresist is formed on the surface of the ILD layer
208
.
FIG. 2B
shows the partially completed semiconductor device
200
as shown in
FIG. 2A
with the layer
212
of photoresist patterned and developed to form a hole
214
in the layer of photoresist that exposes a selected portion of the ILD layer
108
.
FIG. 2C
shows the partially completed semiconductor device
200
as shown in
FIG. 2B
after an etch process (or processes) that etches the ILD layer
208
down to the layer
210
of TiN material, through the layer
210
of TiN material and into the metal structure
204
. As discussed above, it has been found that the etch process that etches part of the metal structure causes residual metal/resist particles, some of which are shown at
213
, to adhere to the walls of the hole
214
. These residual metal/resist particles are extremely difficult to clean from the via and the cleaning process necessitates at least one additional process step.
FIG. 2D
shows the partially completed semiconductor device
200
as shown in
FIG. 2C
with the layer of photoresist removed and a thin layer
216
of a barrier material formed on the walls of the hole
214
. The particles
213
of residue material can cause discontinuities in the barrier layer
216
. These discontinuities can cause the barrier layer to fail and provide a communication between the conductive material that will be used to fill the hole
214
and the surrounding ILD material
208
. The communication between the conductive material and the ILD layer
208
can cause the semiconductor device
200
to fail.
FIG. 2E
shows the partially completed semiconductor device
200
as shown in
FIG. 2D
with the hole
214
filled with a conductive material
218
. The conductive material
218
is typically tungsten but could be another conductive material such as aluminum or copper.
FIGS. 2F-2H
show the partially completed semiconductor device
200
as shown in
FIGS. 2A-2E
showing a manufacturing process that includes a process for clea
Shields Jeffrey A.
Yu Allen S.
Advanced Micro Devices , Inc.
Malsawma Lex H.
Nelson H. Donald
Smith Matthew
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