Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-17
2001-05-15
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S381000
Reexamination Certificate
active
06232175
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88117379, filed Oct. 8, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method of manufacturing the double recess crown-shaped capacitor of a DRAM unit.
2. Description of the Related Art
A capacitor is the ‘heart’ of each dynamic random access memory (DRAM) unit. Data in each DRAM unit is stored as charges inside the capacitor. Hence, the larger the capacity for storing electric charges inside a capacitor, the smaller will be the number of soft errors resulting from external interference such as impinging alpha particles. In addition, a capacitor with a large charge storage capacity can lower the refreshing frequency.
Since the capacitance of a capacitor depends on the surface area of the device, how to maintain sufficient capacitance for conducting normal functions when semiconductor device line width is smaller than 0.25 &mgr;m has become a major problem. One method of increasing the capacitance of a capacitor is to increase its surface area. For a double-recess crown-shaped capacitor, the method of increasing capacitance is to grow a hemispherical silicon grain (HSG) layer on its interior surfaces. Capacitance is increased due to the extra surface provided by the HSG layer.
In general, a double-recess crown-shaped capacitor is formed by first etching a double-recess crown-shaped trench in a silicon oxide layer. A doped polysilicon layer conformal to the surface profile is next formed over the interior surface of the trench and the silicon oxide layer. Hemispherical silicon grain (HSG) is grown on the surface of the doped polysilicon layer. Photoresist is deposited into the trench and over the doped polysilicon layer so that the hemispherical silicon grains on the doped polysilicon layer are protected by a photoresist layer. The photoresist and doped polysilicon to above the silicon oxide layer are remove by etching or chemical-mechanical polishing (CMP) so that neighboring capacitors are isolated. Finally, the photoresist layer and the silicon oxide layer are sequentially removed to form the lower electrode of the double-recess crown-shaped capacitor.
In the aforementioned method of forming the double recess crown-shaped capacitor, the photoresist layer and the silicon oxide layer must be removed using two different processes, thereby increasing processing complexity. Furthermore, if chemical-mechanical polishing is carried out to form the necessary isolation between different capacitors, special equipment must be installed because worn off photoresist particles may adhere to the polishing pad of the chemical-mechanical polishing station, thereby affecting the polishing action.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a double-recess crown-shaped DRAM capacitor with simple processing steps.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a double recess crown-shaped DRAM capacitor. A dielectric layer is formed over a substrate. Using photolithographic and etching techniques, a contact opening is formed in the dielectric layer. A conductive layer is formed over the dielectric layer filling the contact opening to form a conductive plug. A second dielectric layer is formed over the conductive layer. Again using photolithographic and etching techniques, the second dielectric layer is patterned to form a trapezoidal-shaped dielectric layer. An organic bottom anti-reflective coating (organic BARC) is coated over the trapezoidal-shaped dielectric layer and the conductive layer. Organic BARC above the trapezoidal-shaped dielectric layer is removed. Using the organic BARC as an etching mask, the trapezoidal-shaped dielectric layer is etched to form triangular-shaped dielectric layers and a trench in the conductive layer. The residual organic BARC is completely removed. Using the triangular-shaped dielectric layers as a hard etching mask, two types of trenches each having a different depth are formed in the conductive layer. The triangular-shaped dielectric layers are removed to form a double-recess lower electrode. Hemispherical silicon grains are grown over the interior surface of the double-recess lower electrode as well as the external sidewalls. Finally, a conformal dielectric layer and a conformal conductive layer are sequentially formed over the surface of the double-recess lower electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5474951 (1995-12-01), Han et al.
patent: 5668039 (1997-09-01), Lin
Chan Bor-Wen
Liu Yuan-Hung
Huang Jiawei
J.C. Patents
Taiwan Semiconductor Manufacturing Co. Ltd.
Tsai Jey
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