Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1998-12-15

2001-01-30

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S435000

Reexamination Certificate

active

06180467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabricating method of a semiconductor device. More particularly, the present invention relates to a method of forming an isolation region in a semiconductor substrate.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a semiconductor substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the metal oxide semiconductor field effect transistors (MOSFETs) are isolated from each other by isolation regions in order to prevent current leakage among the MOSFETs. As the integration of the integrated circuit increases and the linewidth thereof decreases, it becomes desirable to use a shallow trench isolations (STI) in the integrated circuit.
A shallow trench isolation is commonly used in the manufacture of semiconductor device which is formed by anisotropically etching to form a trench in the substrate, depositing an isolation layer to fill the trench, performing a densification step, and then performing some follow-up steps to form an isolation region. In the above procedures for forming a shallow trench isolation, the densification step is performed with a temperature preferably higher than the glass transition temperature of the isolation layer in order to obtain a glass-like isolation layer which becomes flexible and rubber-like. In other words, the isolation layer becomes more compact after the densification step at a temperature higher than the glass transition temperature of the isolation layer. Additionally, in the densification step, the isolation layer releases the stress from the deposition step of forming the isolation layer.
In the conventional shallow trench isolation method, the isolation layer employed to fill the trench is a non-doped oxide. Since the glass transition temperature of the non-doped oxide layer is above approximately 1000° C. The temperature of the densification step, such as an annealing process, must be above about 900° C., and normally above about 1000° C. However, the high temperature of densification step easily damages specific wafers, such as epitaxial silicon wafers, and increases the thermal budget of the fabricating process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a shallow trench isolation in a semiconductor substrate, wherein the densification step is preformed at a lower temperature.
It is another object of the present invention to provide a method for fabricating a shallow trench isolation in a semiconductor substrate which reduces the thermal budget.
It is further another object of the present invention to provide a method for fabricating a shallow trench isolation in a semiconductor substrate which reduces damage to wafers in a thermal step.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, this invention provides a method of fabricating a shallow trench isolation in a semiconductor substrate. The method includes formation of a mask layer on a substrate. The mask layer is patterned and used as a mask. A portion of the substrate is removed to form the trench in the substrate. A liner layer is formed on the substrate exposed by the trench and optionally, an additional liner layer is formed on the liner layer. A doped isolation layer is formed to fill the trench. A densification step is performed. The mask layer is removed. Since the doped isolation layer has a lower glass transition temperature than that of non-doped isolation employed in the conventional STI method, the temperature of the densification step in the present method is lowered. Therefore, the thermal budget of the fabricating process and the chance of wafer damages are reduced.
In a preferred embodiment of the present invention, the material of the doped isolation layer preferably is an oxide doped with boron (B), phosphorus (P), germanium (Ge), or the combination thereof, or the likes. Preferably, the material of the doped isolation layer is one selected from the group consisting of silicon glass (BSG), phosphate silicon glass (PSG), germanium silicon glass (GeSG), or the combinations thereof, or the like. The glass transition temperature of the doped isolation layer, such as doped oxide layer, is lower than that of the conventional non-doped oxide layer. Therefore, the temperature of the densification step according to the preferred embodiment of this invention is lower than that of the conventional densification step, which is about 700° C. to 1000°C.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
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patent: 5763315 (1998-06-01), Benedict et al.
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patent: 5985735 (1999-11-01), Moon et al.
patent: 5989978 (1999-11-01), Peidous

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