Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-09-07
2001-01-02
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S305000, C438S306000, C438S307000
Utility Patent
active
06168999
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to the fabrication of submicron semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor devices include deep-submicron metal-oxide semiconductor fieldeffect transistors (MOSFET).
FIG. 1
illustrates a conventional cell of a MOSFET. The cell
100
comprises a gate
102
on a substrate
104
. The gate typically comp rises a polysilicon layer
106
with a salicide layer
108
on top. Sidewall spacers
110
comprising oxide protect the gate
106
. The cell
100
also comprises a salicide layer
112
and a silicon nitride layer
114
on the substrate
104
next to the spacers
110
. In the substrate
104
on the source and drain sides are extensions
116
, halo implanted areas
118
, and the source
120
and drain
122
regions. The cell
100
has a lateral symmetric channel doping profile. However, as device dimensions are scaled down to the sub-100 nm regime, the speed of the device is not scaled in the same manner.
Another problem with the conventional MOSFET cell structure is that as devices are scaled down, the source/drain junction becomes more shallow, causing the series resistance to become larger. In order to maintain a low series resistance, the source and drain must be heavily doped. However, when the dopant concentration becomes too high, the strong electric field in the channel which results causes the hot carrier injection phenomenon. This damages the gate and compromises the reliability of the device. Hot carrier injection is well known in the art and will not be further discussed here.
Accordingly, there exists a need for a method of fabrication of a submicron MOSFET which improves the speed of the device while also preventing hot carrier injection. The present invention addresses this need.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, where the spacer facilitates formation of a lateral asymmetric channel; forming heavily doped extensions in the source side and the drain side, where the spacer prevents doping in the spacer area;
removing the spacer; and
forming a lightly doped extension in the drain side, where the heavily doped extensions and the lightly doped extension prevent hot carrier injection. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area. A lateral asymmetric channel is thus formed, and the speed of the submicron MOSFET is increased while simultaneously preventing hot carrier injection.
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Hiroki et al, “A high performance 0.1 micron MOSFET with asymmetric channel profile,” IEEE IEDM pp. 439-442 (1995).
Matsuki et al, “Laterally-doped channel (LDC) structure for sub-quarter micron MOSFETs,” Tech. Dig. Ymp. on VLSI Eech. pp. 113-114(1991).
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Long Wei
Xiang Qi
Advanced Micro Devices , Inc.
Booth Richard
Hack Jonathan
Sawyer Law Group LLP
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