Process for fabricating a common source region in memory...

Details Process for fabricating a common source region in memory... Process for fabricating a common source region in memory...

1998-10-22

2001-04-03

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S513000

Reexamination Certificate

active

06211020

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices and process for fabricating the same and, particularly to a process for fabricating a flash EPROM or EEPROM memory device.
2. Description of the Related Art
Non-volatile memory devices, and particularly so-called “flash” memory devices, have become increasingly more popular in data storage applications. The term EPROM is an acronym for Erasable Programmable Read Only Memory, while EEPROM refers to Electrically Erasable PROMs. The term “flash” in conjunction with electrical erasable programmable read only memory or “flash EEPROMS”, generally refers to EEPROM memory cells which are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. The operation and structure of such devices is discussed in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987, to Mukherjee et al., and IEEE Journal of Solid State Circuitry, Vol. SC-22, No. 5, October, 1987, pages 676-683 in an article entitled, “A 128K Flash EEPROM Using Double Polysilicon Technology” by Gheorghe Samachisa, et al.
Generally, an array of flash EPROM or EEPROM memory cells may be formed on a semiconductor substrate in a series of rows and columns, accessed by conductors referred to as word lines and bit lines. These memory cells are formed in the “core” area of the cell, with control transistors lying in the device's “periphery” region. A portion of an array is illustrated schematically in FIG.
1
. In
FIG. 1
, a two-by-two matrix of memory cells
100
is shown with a first memory cell
20
having its drain connected to bit line
0
(BL
0
), its control gate coupled to word line
0
(WL
0
) and its source floating. Also shown in
FIG. 1
is a second memory cell
22
also having its drain connected to BL
0
, its control gate coupled to word line
1
(WL
1
) and its source floating. As illustrated in
FIG. 1
, the sources of the memory cells
20
,
22
,
24
and
26
are shown to be floating; however, the sources can be connected to form a common source line.
Each memory cell is formed in the semiconductor substrate by, for example, diffusion of an N+ drain region, and an N-type, double diffused source region, with a channel region positioned between the drain and source regions. The double diffused source region is formed of a deeply diffused, but lightly doped N-type region, commonly doped with phosphorous (known as a double diffused junction (DDJ)), and a more heavily doped but more shallowly diffused N+ region, commonly doped with arsenic (As) within the DDJ. A tunnel oxide is formed on the silicon substrate separating a floating gate from the source and drain regions, and a control gate is formed over the floating gate, separated therefrom by an inter-polysilicon dielectric layer.
FIG. 2
illustrates a top view of a portion of a semiconductor substrate under fabrication as a flash cell, such as that shown schematically in FIG.
1
. Shown in
FIG. 2
are two unit cells
20
,
22
, formed by a second polysilicon gate layer or control gate layer (defining wordline (WL)) deposited on top of an interdielectric layer
30
(shown in
FIG. 5
) such as oxide-nitride-oxide sandwich, and a first polysilicon gate layer or floating gate layer
29
. Field oxide regions
42
formed by, for example, a LOCOS process, separate and isolate adjacent memory devices along a word line. A common source region
43
is used for adjacent cells and is formed by a self-aligned source mask and etch, as discussed below. Metal layers
48
or another conductor material used to couple the cells are omitted for clarity.
One conventional method of manufacturing a flash EPROM or EEPROM array includes a number of separate masking steps between the point in time when polysilicon layers (or “poly stack”) which will form control gate and floating gate regions are deposited onto a substrate, and the steps of formation of the core memory devices. (It should be recognized that complete processing of the integrated circuit requires a substantial number of processing steps which are not detailed here in order not to unduly obscure the nature of the present invention. Such processing steps would be within the knowledge and skill of one of average skill in the art.)
In forming flash devices, the source side of the core memory cells can be connected by a common V
ss
buss. The use of such a bus saves die size by allowing designers to have many transistors share a common contact. The resistance of the V
ss
bus determines the number of transistors per contact, i.e., the size and overall performance of the part.
Typically, this bus is formed in a process known as the SAS. In this process, during formation of the integrated circuit device, the field oxide separating the source regions of a number of cells are removed and an implant made into the substrate with an impurity of the same type as formed the source regions to couple the source regions together to form the V
ss
bus.
Typically, the core region in which the memory cells are formed comprises an P-type region, and the source region an N-type implant regions, so that the implant for the self aligned source regions is generally performed by a zero degree arsenic implant.
One drawback of this method is that the Vss bus is pinched off in the area where the etched region steps up to the active regions.
SUMMARY OF THE INVENTION
The invention generally comprises a method for manufacturing a non-volatile memory device. In one aspect, the method includes forming a memory device on the semiconductor substrate by forming isolation regions in said substrate, forming gate stacks on the substrate between respective ones of said isolation regions, with each stack having at least an active region adjacent thereto, and forming common source regions for the plurality of gate stacks through a plasma implant of an impurity.
In a second aspect, a memory device having a plurality of memory transistors is provided. The device generally comprises a semiconductor substrate having a generally planar surface. Field oxide regions are formed in the semiconductor substrate to a depth below the substrate surface. The common bus region is provided which is exposed to the substrate, the common bus region including at least a first recessed portion of the substrate wherein areas of the field oxide regions have been removed so that said recessed portion has a depth below the surface of the substrate. An impurity region forming the common bus is formed in the common bus region, with the impurity region having a junction depth which is generally uniform within the recessed portion.


REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4861729 (1989-08-01), Fuse et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5470773 (1995-11-01), Liu et al.
patent: 5918141 (1999-06-01), Merrill
Yu et al Conformal Doping of High aspect Ratio Techniques By Plasma Immersion Ion Implantation Plasma assisted processing laboratory university of california, berkley, 1991.*
Samachisa et al A 128K Flash EEPROM using Double-Polysilicon Technology IEEE journal of solid state circuits, 1987.*
Samachisa, et al., “A 128K Flash EEPROM Using Double Polysilicon Technology,” IEEE Journal of Solid State Circuitry, vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
Yu, et al., “Conformal Doping of High Aspect Ratio Techniques by Plasma Immersion Ion Implantation (PIII),” Plasma Assisted Materials Processing Laboratory, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720.

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