Method of making a sacrificial self-aligned interconnect...

Details Method of making a sacrificial self-aligned interconnect... Method of making a sacrificial self-aligned interconnect...

1999-04-16

2001-01-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S250000, C438S253000, C438S404000, C438S618000

Utility Patent

active

06168986

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to methods of forming an interconnect structure during integrated circuit fabrication. More particularly, the present invention relates to methods of forming a self-aligned interconnect structure for an integrated circuit. The method of the present invention is particularly useful in forming a self-aligned polysilicon interconnect structure that can be sacrificially etched without damaging an adjacent active region that is provided with electrical communication through the interconnect structure.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
Modern integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a small semiconductor substrate. The conventional semiconductor devices which are formed on the semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
In order to compactly form the semiconductor devices, the semiconductor devices are formed on varying levels of the semiconductor substrate. Consequently one step in the process of manufacturing an integrated circuit is to electrically connect the discrete semiconductor devices that are located on nonadjacent structural levels of the integrated circuit. One manner of electrically connecting these semiconductor devices is with an interconnect structure. The interconnect structure generally comprises a region of conducting material that is formed between the semiconductor devices or portions of the semiconductor devices that are being placed in electrical communication. The interconnect structure serves as a conduit for delivering electrical current between the semiconductor devices. Specific types of interconnect structures include local interconnects, contacts, buried contacts, vias, plugs, and filled trenches. Resistors and diodes also function as interconnect structures when making electrical contact between separate semiconductor devices.
The semiconductor industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the density of devices on the integrated circuits, and to reduce the price of the integrated circuits. To accomplish this task, the semiconductor devices used to form the integrated circuits are continually being increased in number and decreased in dimension in a process known as miniaturization. Interconnect structures and existing processes of forming interconnect structures must in turn be adapted to facilitate the constant miniaturization of the semiconductor devices for which the interconnect structures are used to connect.
One component of the integrated circuit that is becoming highly miniaturized is the active region. The active region is a doped area on a silicon substrate of the semiconductor substrate that is used together with other active regions to form a diode or transistor. The miniaturization of the active region complicates the formation of the interconnect structure in that, in order to maintain sufficient conductivity, the interconnect structure must be formed in exact alignment with the active region. Also, the area of the interconnect structure interfacing with the active region must be maximized. Thus, less area exists as tolerance for misalignment of the interconnect structure.
The active region is also becoming increasingly shallow. Consequently, measures must be taken in forming the interconnect structure and overlying semiconductor device to prevent silicon from the active region from being consumed. This shallowness of the active region often necessitates a planar interconnect structure interface that minimizes penetration of the original active region surface. The shallowness of the active region also often necessitates the use of a material other than the traditionally used aluminum in the interconnect structure for interfacing with the active region. Direct contact with aluminum causes the aluminum to diffuse into the silicon of the active region and to form spikes which can penetrate entirely through the active region, causing adverse electrical consequences.
These demands on the interconnect structure have not been adequately met by the existing conventional technology for forming the interconnect structure. As a result, formation of the interconnect structure is currently a limiting factor in the miniaturization of integrated circuits.
One type of interconnect structure frequently used in the conventional technology is the buried contact. The buried contact is a region of polysilicon that makes direct contact between the interconnect structure and the active region, eliminating the need for a metal link. In forming the buried contact, a window is opened in a thin gate oxide over the active region that the interconnect structure is to electrically connect. Thereafter, polysilicon is deposited in direct contact with the active region in the opening but is isolated from the underlying silicon substrate of the semiconductor substrate by gate oxide and by field oxides everywhere else. An ohmic contact is formed at the polysilicon and active region interface by diffusion into the active region of a dopant present in the polysilicon. This dopant diffusion in to the active region in effect merges the polysilicon with the active region. A layer of insulating film is then deposited to cover the buried contact.
The buried contact is so termed because a metal layer can cross over the active region forming the buried contact without making an electrical connection to the buried contact. The use of a buried contact eliminates spiking and provides an additional benefit in that it makes available an additional level for forming interconnect structures on the integrated circuit. This additional level allows circuit connections to be formed in one step and then in a later step to be connected with surface level metal interconnect lines. The additional level also adds significant interconnect structure routing flexibility to the integrated circuit design.
The buried contact also exhibits certain shortcomings. For instance, it is difficult at greater miniaturization levels to exactly align the contact hole with the active region when patterning and etching the contact hole. As a result, topographies near the active area can be penetrated and damaged during etching of the contact hole. For example, a misaligned buried contact hole etch can notch and therefore damage a gate stack. The damage reduces the performance of the active region and neighboring structures which causes a loss of function of the semiconductor device being formed and possibly a defect condition in the entire integrated circuit. To remedy the problems associated with the buried contact the prior art uses compensation techniques such as an etch stop barrier. These compensation techniques are time consuming and thus reduce throughput.
The active region is also, in order to compensate for the aforementioned complications, typically constructed with larger dimensions. As a result, the degree to which the active region can be miniaturized under the conventional technology is limited.
One improvement in conventional interconnect structures is the silicided contact. Fo

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