Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-30
2001-03-13
Fahmy, Wael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S184000, C438S183000, C438S230000, C438S164000, C438S197000, C438S240000
Reexamination Certificate
active
06200866
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
This invention relates to the manufacture of integrated circuits, and specifically to the manufacture of MOSFET devices formed using a replacement gate.
Manufacturing of MOSFET semiconductors is well known in the art. Such structures are shown in U.S. Pat. No. 4,702,792 to Chow et al., which discloses a technique for making conductive channels of small size.
The replacement or “cast” process is a good candidate for fabricating transistors with a wide selection of gate materials. Due to the process controllability issues in current technology, however, the process is not widely used. The main obstacle to using the replacement gate process is control of the gate critical dimension during the gate replacement process.
Chatterjee et al. have written on the replacement gate process, specifically the use of polysilicon as the replacement gate material, in the IEDM Tech. Digest, page 777, 1998. The disadvantage of using polysilicon as the replacement gate material is the difficulty in removing the polysilicon using a wet-etch process that is selective over silicon dioxide.
Yagishita et al. have also written on the replacement gate process in the IEDM Tech. Digest, page 785, 1998. Yagishita also discloses the use of polysilicon as the replacement gate material.
Evans et al., in patent application Ser. No. 09/028,157, filed Feb. 23, 1998, of which this application is a continuation-in-part, discloses the use of silicon nitride as a replacement gate material. Using silicon nitride as the replacement gate material is effective but patterning the silicon nitride replacement gate using a dry etch process can be difficult. To optimize dry silicon nitride etch it is necessary that the etchant be selective over both silicon and silicon dioxide.
Heretofore, silicon germanium and other Group IV-B (Periodic Table—copyright© Sargent-Welch Scientific Company, 1979) elemental alloys have not been used as a dummy, or replacement, gate during the fabrication of a MOSFET device.
It would be advantageous to have a replacement gate MOSFET fabrication process with improved etch selectivity between the replacement gate material and the adjacent materials used in the spacers and other structures. Although the aforementioned references discuss the fabrication of a MOSFET device, they do not provide the advantages of the instant invention.
An object of the invention is to provide a method of manufacturing a MOSFET device wherein the source region and the drain region are formed before formation of the gate.
Another object of the invention is to provide a MOSFET device that may be constructed on both conventional silicon and silicon-on-insulator (SOI) substrates.
A further object of the invention is to provide for the fabrication of a MOSFET device that allows the use of any type of gate dielectric material.
Still another object of the invention is to provide for the fabrication of a MOSFET device having a highly conductive material, such as refractory metal or copper, as the gate electrode.
A further object of the invention is to provide for the fabrication of a MOSFET device wherein the fabrication process allows increased controllability of the etch process to achieve a desired critical dimension of the gate.
Accordingly, the method of the invention includes: forming a silicon germanium, or similar alloy island, the materials of the alloy being preferably selected from the elements of Group IV-B of the Periodic Table of Elements, above a gate region in the substrate; building an oxide or a nitride sidewall about the silicon germanium island (silicon germanium is used herein as a representative example of the preferred alloy of Group IV-B elements to be used); forming a source region and a drain region in the substrate; removing the silicon germanium island, without removing the sidewall around the island, thereby leaving a void over the gate region; and filling the void with a gate structure by steps which preferably include: forming a gate dielectric over the gate region in the void, and filling the remainder of the void with gate electrode material.
The step of removing the silicon germanium (or other Group IV-B alloy) island preferably includes depositing, over the island and the areas over the source region and the drain region, a non-island-material layer that permits the alloy of the island to be selectively dissolved or otherwise removed without simultaneously removing the non-island-material layer which was deposited. The non-island-material layer can be either polysilicon (alternatively known to those skilled in the art as polycrystalline silicon), when raised source/drain regions are to be provided, or a suitable dielectric such as silicon nitride or oxide, when conventional source/drain regions are provided. Following the filling of the void with a gate structure, the method preferably includes planarizing the upper surface of the structure by chemical mechanical polishing. In the embodiment of the invention wherein raised source/drain regions are formed, the method further preferable includes; depositing a metal layer on the upper surface of the structure; and metallizing the structure to form electrodes in electrical contact with the source region, the gate region, and the drain region.
REFERENCES:
patent: 5856225 (1999-01-01), Lee et al.
patent: 5858843 (1999-01-01), Doyle et al.
patent: 5955759 (1999-09-01), Ismail et al.
Article entitled “CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator” presented at Int'l Electron Devices Mtg., 12-6,9-98, by Chatterjee, et al., pp 29.2.2-29.1.4.
Article entitled “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1&mgr;m Regime” presented at Int'l Electron Devices Mtg., 12-6,9-98, by Yagishita, et al., pp 29.3.1-29.3.4.
Article entitled A Polycrystalline SiGe Gate CMOS Technology, presented by Int'l Electron Devices Mtg., 12-6,9-98, by King, et al., pp 10.4.1-10.4.4.
Article entitled Enhancement of PMOS Device Performance with Poly-SiGe Gate, published in IEEE Electron Device Ltrs., vol. 20, No. 5, May 1999, by Lee, et al., pp 232-234.
Article entitled Selective Removal of SiGe from (100) Si Using HNO3and HF, published in J. Electrochem Soc., vol. 139, No. 10, Oct. 1992, pp 2943-2947.
Article entitled “Etching Characteristics of SiGe Alloy in Ammociac Wet Cleaning”, published in Appl. Phys. Lett. 57(21) Nov. 1990, pp 2202-2204.
Evans David R.
Ma Yanjun
Ono Yoshi
Tweet Douglas J.
Fahmy Wael
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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