Methods and systems for testing integrated circuit memory...

Details Methods and systems for testing integrated circuit memory... Methods and systems for testing integrated circuit memory...

1999-10-08

2001-09-11

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

06288955

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices, and more particularly to methods and systems for testing integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, more memory cells may be included in each memory device. This increase in the number of memory cells in an integrated circuit memory device can make the testing thereof more time consuming and complex.
FIG. 1
is a block diagram of a conventional integrated circuit memory device testing system (apparatus). As shown in
FIG. 1
, a pattern generator
4
outputs a test pattern that is written in a memory to be tested, also referred to as Device Under Test (DUT)
10
. The pattern generator
4
also provides an address to designate a position for the test pattern. The pattern generator
4
also outputs a desired value pattern. The desired value pattern is provided to a logic comparator
3
. The logic comparator
3
preferably comprises a digital comparator that compares the desired value pattern with the test pattern that is read from the DUT
10
.
When the logic comparator
3
detects a defect resulting from failure of a comparison test, the results of the comparison test are written into a corresponding address of a defect interpretation memory
7
. Accordingly, the defect interpretation memory
7
preferably contains the defect information at the address of a memory cell that has the defect. The defect interpretation memory preferably has the same memory cell structure as that of the DUT
10
. A testing unit, also referred to as a testing Central Processing Unit (CPU)
9
, generates control signals to control the logic comparator
3
, the pattern generator
4
and the defect interpretation memory
7
.
In order to test the DUT
10
, a test pattern from the pattern generator
4
is written into the DUT
10
by designating an address, under control of the testing CPU
9
. The test pattern is read from the DUT
10
and is provided to the logic comparator
3
along with the desired value pattern that is provided by the pattern generator. If these patterns are not identical, a defect is detected. The defect information is memorized at the corresponding address of the defect interpretation memory
7
. After memorizing the defect information about the DUT
10
, the testing CPU
9
interprets the defect in order to, for example, substitute redundant memory cells for defective memory cells.
Therefore, in conventional testing of integrated circuit memory devices, an integrated circuit memory device is tested in a time division manner, wherein comparison tests between test pattern data that is input into a memory and resultant data that is output from the memory are performed, the results of the comparison test are loaded into a defect interpretation memory and then the results of the comparison test are analyzed. Unfortunately, these conventional testing methods may be excessively time consuming. The testing time may be further exacerbated as the size of integrated circuit memory devices continues to increase.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved systems and methods for testing integrated circuit memory devices.
It is another object of the present invention to provide systems and methods that can increase the testing speed of integrated circuit memory devices.
These and other objects can be provided, according to the present invention, by loading results of a succeeding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device, while simultaneously analyzing results from a preceding comparison test. It will be understood that the terms “preceding” and “succeeding” are relative terms to one another and do not require immediately preceding or immediately succeeding. Either the preceding or succeeding comparison test may be regarded as a current comparison test.
More specifically, a first defect interpretation memory is loaded with the results of a succeeding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Simultaneously, results from a preceding comparison test are analyzed in a second defect interpretation memory. Subsequently, the results of the succeeding comparison test can be analyzed in the first defect interpretation memory while simultaneously loading the results of a next succeeding comparison test in the second defect interpretation memory.
The loading and simultaneous analysis may be performed under control of a testing unit, and the analyzing may take place in a defect interpreting unit. The first and second defect interpretation memories may be separate memories or may comprise respective first and second portions of a defect interpretation memory. The defect interpretation unit and the testing unit may be separate units or may comprise respective first and second portions of a processing unit.
Parallel testing methods and systems of the present invention can test integrated circuit memory devices more rapidly than conventional serial testing. In particular, conventional systems generally load results of a comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device, into a defect interpretation memory. Then, the results were read from the defect interpretation memory and interpreted afterwards. Accordingly, testing and defect interpreting were performed serially in a time division process.
This time division process may consume excessive time because the comparison test first is performed and the results are stored in a defect interpretation memory. Then, the defect can be interpreted by a testing CPU. As the integration density of integrated circuit memories continues to increase, longer times may be used to test the memory using conventional time division methods. In sharp contrast, the present invention can simultaneously load results of a succeeding comparison test while analyzing results from a preceding comparison test. Accordingly, these processes may take place in parallel, to allow reduced time for testing.
More specifically, according to the present invention, integrated circuit memory devices are tested by loading into a first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Automatic switching then takes place to a second defect interpretation memory. The results of a succeeding comparison test are loaded therein, while simultaneously analyzing results from the preceding comparison test in the first defect interpretation memory. Then, automatic switching back to the first defect interpretation memory takes place, and results of a next succeeding comparison test are loaded therein while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory. Automatic switching and automatic switching back are repeatedly performed, to thereby simultaneously test a memory device and analyze memory test results.
When automatically switching to a second defect interpretation memory and loading therein results of a succeeding comparison test, the first defect interpretation memory may be automatically connected to a defect interpreting unit, to simultaneously analyze the results from the preceding comparison test in the first defect interpretation memory. Moreover, when automatically switching back to the first defect interpretation memory and loading therein results of a next succeeding comparison test, the second defect interpretation memory may be automatically connected to the defect interpreting unit, to simultaneously analyze the results from the succeeding comparison test in the second defect interpretation memory.
Thus

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